From: Andi Kleen <ak@suse.de>
To: john stultz <johnstul@us.ibm.com>
Subject: Re: Keyboard Stuttering
Date: Mon, 16 Oct 2006 12:59:02 +0200
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Cc: Lee Revell <rlrevell@joe-job.com>,
       Dmitry Torokhov <dmitry.torokhov@gmail.com>,
       Frank Sorenson <frank@tuxrocks.com>, linux-kernel@vger.kernel.org,
       David Gerber <dg-lkml@zapek.com>
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On Friday 13 October 2006 22:45, john stultz wrote:
> On Thu, 2006-10-12 at 12:12 -0400, Lee Revell wrote:
> > On Tue, 2006-10-10 at 11:25 -0700, john stultz wrote:
> > > On Tue, 2006-10-10 at 13:09 -0400, Dmitry Torokhov wrote:
> > > > > Same problem here. Intel Core 2 Duo with 2.6.19-rc1 x86_64 SMP. Happens on
> > > > > 2.6.17 too. I use 'noapic' as a workaround but that disables one of the CPU
> > > > > core of course.
> > > > >
> > > > > I cannot reproduce the problem within the console nor gdm. Only on the X
> > > > > desktop.
> > > > >
> > > > 
> > > > It looks like the only clocksource available on David's box is
> > > > "jiffies" although the processor shows that it supporst tsc and PM
> > > > timer is enabled and I think that this is what causes keyboard
> > > > stuttering in X. See http://bugzilla.kernel.org/show_bug.cgi?id=7291.
> > > > I believe clocksources is your turf, could you please take a look at
> > > > this.
> > > 
> > > Sure thing. I followed up in the bug, but I don't think the clocksource
> > > code is involved. x86_64 hasn't converted to GENERIC_TIME, so jiffies is
> > > what we use to increment xtime, but the TSC, ACPI PM, or HPET is used
> > > for gettimeofday, etc. 
> > > 
> > > I suspect C3 idling is the culprit, since noapic works around the issue.
> > 
> > Wait, does this mean that Intel's x86-64 implementation has the same
> > buggy TSC as AMD's?
> 
> Not the same issue, no.. but the TSCs do halt in lower powersaving
> modes, which can cause similar results. The new TSC clocksource code on
> i386 will disqualify itself if those lower powerstates are entered, so
> it should auto detect and fall back. On x86_64, this logic apparently is
> sill needed.

x86-64 has code to not use TSC when there is C3. And special case
code for some big boxes which don't sync the TSC fully.

AFAIK the logic is correct.

There were a few failures, but they were either totally broken BIOS or 
overclocking (some ways of overclocking seem to break the TSC synchronization
on dual die Intel dual core CPUs)

Overclocking is not supported (and those people who want it can use notsc) 
and the broken BIOS cases were all fixed with a BIOS update

-Andi


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