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Thu, 15 Apr 2021 04:15:06 -0700 Envelope-to: git@xilinx.com, saikrishna12468@gmail.com, robh+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.23.64.106] (port=52540 helo=xhdvnc125.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lWzxh-0002yB-4S; Thu, 15 Apr 2021 04:15:05 -0700 Received: by xhdvnc125.xilinx.com (Postfix, from userid 14964) id 4D385122169; Thu, 15 Apr 2021 16:45:04 +0530 (IST) From: Sai Krishna Potthuri To: Linus Walleij , Rob Herring , Michal Simek , "Greg Kroah-Hartman" CC: , , , , , , Sai Krishna Potthuri Subject: [PATCH v5 0/3] Add ZynqMP pinctrl driver Date: Thu, 15 Apr 2021 16:43:10 +0530 Message-ID: <1618485193-5403-1-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com> X-Mailer: git-send-email 2.1.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bce30c8c-61bd-47b6-6abd-08d8ffffc397 X-MS-TrafficTypeDiagnostic: BYAPR02MB5558: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:513; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2021 11:15:23.5355 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bce30c8c-61bd-47b6-6abd-08d8ffffc397 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT003.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB5558 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for Xilinx ZynqMP pinctrl driver and also update the Xilinx firmware driver to support pinctrl functionality. This driver queries the pin information from the firmware and allow configuring the pins as per the request. changes in v5: - Used generic property 'power-source' instead of driver specific for configuring the IO voltages, updated the same in dt-binding. - Added support to build driver as a module. - Used error codes returned by the Xilinx firmware instead of shadowing the error codes in the driver. - Fixed comments from Andy related to spell checks, NULL checks, explicit typecast, header inclusion ordering, removing kernel docs for the obvious ones. changes in v4: - Added comment for ignoring the return value for GET_FUNCTION_NAME qid. - Updated the zynqmp_pinctrl_get_function_name() API prototype to void as it always returns zero. changes in v3: - Fixed binding doc comments from Rob. - Used 'maxItems' for groups and pins properties. - Updated commit subject and description to have present tense statements. changes in v2: - Use pattern for pin names in yaml file. - Updated to support multiple groups and pins. - Added type ref for the vendor specific properties. - Removed 'schmitt-cmos', instead used common properties. - Removed macros for drive-strength property. Sai Krishna Potthuri (3): firmware: xilinx: Add pinctrl support dt-bindings: pinctrl: Add binding for ZynqMP pinctrl driver pinctrl: Add Xilinx ZynqMP pinctrl driver support .../bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml | 336 +++++++ drivers/firmware/xilinx/zynqmp.c | 114 +++ drivers/pinctrl/Kconfig | 14 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-zynqmp.c | 906 ++++++++++++++++++ include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 19 + include/linux/firmware/xlnx-zynqmp.h | 90 ++ 7 files changed, 1480 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml create mode 100644 drivers/pinctrl/pinctrl-zynqmp.c create mode 100644 include/dt-bindings/pinctrl/pinctrl-zynqmp.h -- 2.17.1