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Peter Anvin" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "K. Y. Srinivasan" , x86@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hyperv@vger.kernel.org Subject: [PATCH v2 5/7] KVM: SVM: hyper-v: Remote TLB flush for SVM Date: Thu, 15 Apr 2021 13:43:40 +0000 Message-Id: <959f6cc899a17c709a2f5a71f6b2dc8c072ae600.1618492553.git.viremana@linux.microsoft.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable remote TLB flush for SVM. Signed-off-by: Vineeth Pillai --- arch/x86/kvm/svm/svm.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 2ad1f55c88d0..de141d5ae5fb 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include "trace.h" @@ -44,6 +45,8 @@ #include "svm.h" #include "svm_ops.h" +#include "hyperv.h" + #define __ex(x) __kvm_handle_fault_on_reboot(x) MODULE_AUTHOR("Qumranet"); @@ -931,6 +934,8 @@ static __init void svm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); } +static struct kvm_x86_ops svm_x86_ops; + static __init int svm_hardware_setup(void) { int cpu; @@ -1000,6 +1005,16 @@ static __init int svm_hardware_setup(void) kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G); pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis"); +#if IS_ENABLED(CONFIG_HYPERV) + if (ms_hyperv.nested_features & HV_X64_NESTED_ENLIGHTENED_TLB + && npt_enabled) { + pr_info("kvm: Hyper-V enlightened NPT TLB flush enabled\n"); + svm_x86_ops.tlb_remote_flush = kvm_hv_remote_flush_tlb; + svm_x86_ops.tlb_remote_flush_with_range = + kvm_hv_remote_flush_tlb_with_range; + } +#endif + if (nrips) { if (!boot_cpu_has(X86_FEATURE_NRIPS)) nrips = false; @@ -1120,6 +1135,21 @@ static void svm_check_invpcid(struct vcpu_svm *svm) } } +#if IS_ENABLED(CONFIG_HYPERV) +static void hv_init_vmcb(struct vmcb *vmcb) +{ + struct hv_enlightenments *hve = &vmcb->hv_enlightenments; + + if (npt_enabled && + ms_hyperv.nested_features & HV_X64_NESTED_ENLIGHTENED_TLB) + hve->hv_enlightenments_control.enlightened_npt_tlb = 1; +} +#else +static inline void hv_init_vmcb(struct vmcb *vmcb) +{ +} +#endif + static void init_vmcb(struct vcpu_svm *svm) { struct vmcb_control_area *control = &svm->vmcb->control; @@ -1282,6 +1312,8 @@ static void init_vmcb(struct vcpu_svm *svm) } } + hv_init_vmcb(svm->vmcb); + vmcb_mark_all_dirty(svm->vmcb); enable_gif(svm); @@ -3975,6 +4007,11 @@ static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root, svm->vmcb->control.nested_cr3 = cr3; vmcb_mark_dirty(svm->vmcb, VMCB_NPT); +#if IS_ENABLED(CONFIG_HYPERV) + if (kvm_x86_ops.tlb_remote_flush) + kvm_update_arch_tdp_pointer(vcpu->kvm, vcpu, cr3); +#endif + /* Loading L2's CR3 is handled by enter_svm_guest_mode. */ if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) return; -- 2.25.1