Received: by 2002:a05:6a10:17d3:0:0:0:0 with SMTP id hz19csp1187587pxb; Thu, 15 Apr 2021 16:49:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxqjzSr8NMcqkqFpvsU27zhixrlfmHUIH8vE0PECP049Hf3kGG9KPC09cpNyvhCi15j2F4L X-Received: by 2002:a63:c66:: with SMTP id 38mr5697085pgm.69.1618530566818; Thu, 15 Apr 2021 16:49:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618530566; cv=none; d=google.com; s=arc-20160816; b=ZVUkBt28lwSeDOWEQ2lNIF/DSp6e4TKjf1CgmiZtYFU5f3MFqwUwyb4XsMn3qpCS5q HHtHCVRNsZYEvfqUmGmxDLFlpQ+hzAOXK45HijWHA9Eo+54SHN7aCF2a18X7RaMyeqWj tye722TJ63eFD23kxjvpZPpR4W3Nu2mbU3mM9AvlueXP3DQ0cceqjDtfLo0MiNI5cVsn vEbBShofjw9xXgUQim1sWJhCYfevrYwnqtF9cajkp4CHJUGKFD0xaaSfzh/KDqDWA1J5 iPT3JOplBt0P/DfGdpmd+3nvBKF+rL3oR3BcgZu82B/m3Pz1bgag3CcAbRcNavbF65KH Xj3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date; bh=RSK8YxkaOqjvo2O5+ok0tzi0yKlKDUGp9KfYtGQQX1g=; b=NxmEXaMKBvy5mWYDk76tOSNc1YD0DB2X/svjfwfURWzcTd0ZYkxkHz8wQznsepDNaj 5vsNY8rwGlTPHdq/1F99AriHupDWwDe2goz2NxUY+AZ9t87Ub5w+8eY0pPpaFRMoeKD9 yIWWyNlCR02FiQYe17rr6+PKeekJYymG0Zgk7q0hkcsKLRLSlCX+41LycP1LOQRwpx/L gosXZgE+2xVu3u9BW0aWFuDqaQZc4cs1z2NqYWpv4Kn3UrORMT06Ggz/+wSfhLkuRUoM RfcBW+PjwDhFKFSFz4aeGJNZswMGhNcMXrh+qW+zOdIR29XVojQmw5IsapaSV3upNOiM rVlQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u13si5486845pgf.212.2021.04.15.16.49.14; Thu, 15 Apr 2021 16:49:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235883AbhDOW5A (ORCPT + 99 others); Thu, 15 Apr 2021 18:57:00 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:54402 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234949AbhDOW5A (ORCPT ); Thu, 15 Apr 2021 18:57:00 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1lXAuQ-00GyOH-LW; Fri, 16 Apr 2021 00:56:26 +0200 Date: Fri, 16 Apr 2021 00:56:26 +0200 From: Andrew Lunn To: "Radu Pirea (NXP OSS)" Cc: hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, kuba@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/2] phy: nxp-c45: add driver for tja1103 Message-ID: References: <20210415092538.78398-1-radu-nicolae.pirea@oss.nxp.com> <20210415092538.78398-3-radu-nicolae.pirea@oss.nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210415092538.78398-3-radu-nicolae.pirea@oss.nxp.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > +config NXP_C45_TJA11XX_PHY > + tristate "NXP C45 TJA11XX PHYs" > + help > + Enable support for NXP C45 TJA11XX PHYs. > + Currently supports only the TJA1103 PHY. > +#define PHY_ID_BASE_T1 0x001BB010 It would be better to use PHY_ID_TJA_1103 here. > + > +#define PMAPMD_B100T1_PMAPMD_CTL 0x0834 > +#define B100T1_PMAPMD_CONFIG_EN BIT(15) > +#define B100T1_PMAPMD_MASTER BIT(14) > +#define MASTER_MODE (B100T1_PMAPMD_CONFIG_EN | \ > + B100T1_PMAPMD_MASTER) You would normally align this with the B100T1_PMAPMD_CONFIG_EN > +static int nxp_c45_reset_done(struct phy_device *phydev) > +{ > + return !(phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL) & > + DEVICE_CONTROL_RESET); > +} > + > +static int nxp_c45_reset_done_or_timeout(struct phy_device *phydev, > + ktime_t timeout) > +{ > + ktime_t cur = ktime_get(); > + > + return nxp_c45_reset_done(phydev) || ktime_after(cur, timeout); > +} > + > +static int nxp_c45_soft_reset(struct phy_device *phydev) > +{ > + ktime_t timeout; > + int ret; > + > + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, > + DEVICE_CONTROL_RESET); > + if (ret) > + return ret; > + > + timeout = ktime_add_ns(ktime_get(), RESET_POLL_NS); > + spin_until_cond(nxp_c45_reset_done_or_timeout(phydev, timeout)); phy_read_mmd_poll_timeout() i think does what you need. > + if (!nxp_c45_reset_done(phydev)) { > + phydev_err(phydev, "reset fail\n"); > + return -EIO; > + } > + return 0; > +} > +static struct phy_driver nxp_c45_driver[] = { > + { > + PHY_ID_MATCH_MODEL(PHY_ID_BASE_T1), > + .name = "NXP C45 BASE-T1", "NXP C45 TJA1103" Andrew