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Date:   Fri, 16 Apr 2021 11:44:26 +0200
From:   Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
To:     Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Thierry Reding <thierry.reding@gmail.com>,
        Lee Jones <lee.jones@linaro.org>, devicetree@vger.kernel.org,
        linux-pwm@vger.kernel.org, punit1.agrawal@toshiba.co.jp,
        yuji2.ishikawa@toshiba.co.jp, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 2/2] pwm: visconti: Add Toshiba Visconti SoC PWM
 support
Message-ID: <20210416094426.x4gyw3drp2fcwczs@pengutronix.de>
References: <20210409230837.1919744-1-nobuhiro1.iwamatsu@toshiba.co.jp>
 <20210409230837.1919744-3-nobuhiro1.iwamatsu@toshiba.co.jp>
 <20210410135321.oissremqropvrpd3@pengutronix.de>
 <20210412025536.i5chpp6sighunvfx@toshiba.co.jp>
 <20210412070232.6q3cgqvuj53p4cmi@pengutronix.de>
 <20210416080721.oa7xdvu22w2b2rkf@toshiba.co.jp>
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Hello Nobuhiro,

On Fri, Apr 16, 2021 at 05:07:21PM +0900, Nobuhiro Iwamatsu wrote:
> On Mon, Apr 12, 2021 at 09:02:32AM +0200, Uwe Kleine-K=F6nig wrote:
> > On Mon, Apr 12, 2021 at 11:55:36AM +0900, Nobuhiro Iwamatsu wrote:
> > > On Sat, Apr 10, 2021 at 03:53:21PM +0200, Uwe Kleine-K=F6nig wrote:
> > > > Can you please put a paragraph analogous to the one in pwm-sifive i=
n the
> > > > same format. This simplified keeping an overview about the oddities=
 of
> > > > the various supported chips.
> > >=20
> > > OK, I will check pwm-sifive's, and add.
>=20
> I will add the following :
>=20
>  * Limitations:
>  * - PIPGM_PWMC is a 2-bit divider (00: 1, 01: 2, 10: 4, 11: 8) for the i=
nput
>  *   clock running at 1 MHz.

I would strip that to:

 - Fixed input clock running at 1 MHz

>  * - When the settings of the PWM are modified, the new values are shadow=
ed
>  *   in hardware until the PIPGM_PCSR register is written and the current=
ly
>  *   running period is completed. This way the hardware switches atomical=
ly
>  *   from the old setting to the new.
>  * - Disabling the hardware completes the currently running period and ke=
eps
>  *   the output at low level at all times.

This looks fine.
=20
> > For me the critical (and only) difference between "off" and
> > "duty cycle =3D 0" is that when a new configuration is to be applied. In
> > the "off" state a new period can (and should) start immediately, while
> > with "duty_cycle =3D 0" the rising edge should be delayed until the
> > currently running period is over.[1]
> >=20
> > So the thing to do here (IMHO) is:
> >=20
> > Iff with PIPGM_PCSR =3D 0 configuring a new setting (that is finalized
> > with writing a non-zero value to PIPGM_PCSR) completes the currently
> > running period, then always assume the PWM as enabled.
>=20
> Yes, this device works that way.

OK, then please use

	state->enabled =3D true

unconditionally in visconti_pwm_get_state().

Best regards
Uwe

--=20
Pengutronix e.K.                           | Uwe Kleine-K=F6nig            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

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