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From:   =?UTF-8?Q?Kornel_Dul=C4=99ba?= <mindal@semihalf.com>
Date:   Fri, 16 Apr 2021 13:36:28 +0200
Message-ID: <CAKpxNiySoggtGdy784evjFWzErikSdp7JxV5z05i7Dc51c3MMg@mail.gmail.com>
Subject: Re: [PATCH] arm64: dts: fsl-ls1028a: Correct ECAM PCIE window ranges
To:     linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Cc:     shawnguo@kernel.org, leoyang.li@nxp.com, robh+dt@kernel.org,
        Marcin Wojtas <mw@semihalf.com>,
        Tomasz Nowicki <tn@semihalf.com>, upstream@semihalf.com
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Hi,

On Wed, Apr 7, 2021 at 2:35 PM Kornel Duleba <mindal@semihalf.com> wrote:
>
> Currently all PCIE windows point to bus address 0x0, which does not match
> the values obtained from hardware during EA.
> Replace those values with CPU addresses, since in reality we
> have a 1:1 mapping between the two.
>
> Signed-off-by: Kornel Duleba <mindal@semihalf.com>
> ---
>  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index 262fbad8f0ec..85c62a6fabb6 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -994,19 +994,19 @@ pcie@1f0000000 { /* Integrated Endpoint Root Complex */
>                         msi-map = <0 &its 0x17 0xe>;
>                         iommu-map = <0 &smmu 0x17 0xe>;
>                                   /* PF0-6 BAR0 - non-prefetchable memory */
> -                       ranges = <0x82000000 0x0 0x00000000  0x1 0xf8000000  0x0 0x160000
> +                       ranges = <0x82000000 0x1 0xf8000000  0x1 0xf8000000  0x0 0x160000
>                                   /* PF0-6 BAR2 - prefetchable memory */
> -                                 0xc2000000 0x0 0x00000000  0x1 0xf8160000  0x0 0x070000
> +                                 0xc2000000 0x1 0xf8160000  0x1 0xf8160000  0x0 0x070000
>                                   /* PF0: VF0-1 BAR0 - non-prefetchable memory */
> -                                 0x82000000 0x0 0x00000000  0x1 0xf81d0000  0x0 0x020000
> +                                 0x82000000 0x1 0xf81d0000  0x1 0xf81d0000  0x0 0x020000
>                                   /* PF0: VF0-1 BAR2 - prefetchable memory */
> -                                 0xc2000000 0x0 0x00000000  0x1 0xf81f0000  0x0 0x020000
> +                                 0xc2000000 0x1 0xf81f0000  0x1 0xf81f0000  0x0 0x020000
>                                   /* PF1: VF0-1 BAR0 - non-prefetchable memory */
> -                                 0x82000000 0x0 0x00000000  0x1 0xf8210000  0x0 0x020000
> +                                 0x82000000 0x1 0xf8210000  0x1 0xf8210000  0x0 0x020000
>                                   /* PF1: VF0-1 BAR2 - prefetchable memory */
> -                                 0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000
> +                                 0xc2000000 0x1 0xf8230000  0x1 0xf8230000  0x0 0x020000
>                                   /* BAR4 (PF5) - non-prefetchable memory */
> -                                 0x82000000 0x0 0x00000000  0x1 0xfc000000  0x0 0x400000>;
> +                                 0x82000000 0x1 0xfc000000  0x1 0xfc000000  0x0 0x400000>;
>
>                         enetc_port0: ethernet@0,0 {
>                                 compatible = "fsl,enetc";
> --
> 2.31.1
>

Have you had a chance to to review the patch? Any questions or remarks?

Regards,
Kornel