Received: by 2002:a05:6a10:17d3:0:0:0:0 with SMTP id hz19csp444945pxb; Fri, 16 Apr 2021 09:18:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzD29nSZoaYv+3SE9XSY80AuNW0J5hCks44RXFKcpwxTXqqfw+3lN2Yp3Ed022CgmvRiKvR X-Received: by 2002:a17:906:6d01:: with SMTP id m1mr9325382ejr.501.1618589907611; Fri, 16 Apr 2021 09:18:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618589907; cv=none; d=google.com; s=arc-20160816; b=ugRzvMVzqwzjm/O7mLERB0OLOoB/SlLIv6Yk0c8cJesk04frr/FAWf9TvqdIZoUPma IkJ/1I8kfhqPmqlA49yyau7041cnNWSOiNLwihvAYhkTXdquJjAaewY3RwYgC++XpNKT 02AZoGZvHs9Vi+j8nAml0orviWvqu1Bj8MGSKBmw9iIjMvqW9l4zPOUEKYFvBHXTBWKV zxK51t+XqQEZXV38i0vCSRwGD9RhHpC4Qi50huqBgPfOjV6shIg2LW9gFbV0+75sakU3 LEvi5r7j+I9CpaITflpqQFYMIHiBECsHlHBK2/two8wxCCM0bhJbGDt2bltHKQX3cx6S RWZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:content-language :in-reply-to:mime-version:user-agent:date:message-id:from:references :cc:to:subject:dkim-signature; bh=Bw/LpDxwLjnc9O3u0xRK0A8jPAhQBjd5ZdY8L9kkF84=; b=XcmR12lrjtayfvu8NmK5ty3JYCbfoG3yAa7Gf1Ef/sa1rSgv2K+7WBxuVlrB/DLvzY jKYwmr335gX4bsARWJyjwScNlgrx7QS4E69y72/9XvR7VhgQo40M2ss3EnpGYqHlWzF8 JAMJ9L4oxPEYtJ7wZgI37RVQA0sE9U7TpkrFusW7txgD3x2kOWE9tuFoyCZDN+SMpbEx yK+GklIXKlC9+LB4Ua6S+9y9BMbGQ0noCDyheXKcRrvUNQSKDzooNYXTk62BfpM3PGOi ViG/Cnr57gFl0UjA/Xh693T2Ewu3cV2hiFBDr0t6vqNYKQibqBTaRvq/k/FAZ41FuqtX iGdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=uqm2U4Fe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i26si5168841edx.43.2021.04.16.09.18.03; Fri, 16 Apr 2021 09:18:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=uqm2U4Fe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235832AbhDPPxp (ORCPT + 99 others); Fri, 16 Apr 2021 11:53:45 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:24842 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S235676AbhDPPxl (ORCPT ); Fri, 16 Apr 2021 11:53:41 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13GFatue019016; Fri, 16 Apr 2021 17:52:53 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=subject : to : cc : references : from : message-id : date : mime-version : in-reply-to : content-type : content-transfer-encoding; s=selector1; bh=Bw/LpDxwLjnc9O3u0xRK0A8jPAhQBjd5ZdY8L9kkF84=; b=uqm2U4FehdigsCmM3+wpsxjknXqR6NPeGCmC9dN8J+VdCulrsYFNlqGjdA+h+3Utwx+7 pNbrBOYaYhv7TUByNtLDLkCAZCxReTtanwjbwX5AP9qD1Vh4Vjk1GRVKCL1mCR9K9BSO OnlYC6Kao61roNJFNJ4M7MaNKE25Lu2Q2+A5n5UUP1V6dN15WANSJzUnw/0zoT5ni1Ub bBDOTGKZM1pwdo0ebFAmgO8OaAUR10E19nVo8KaJJ+SYoqGSJAT9COOaMN6P//sC+VNR mHvFqV4oVNt9muK5JU4OAjt8fNJhg/TORyC8kZROgcUDkK9chXpWSFyhjhONZ7xAb8ZR lQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 37y0g84ehy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Apr 2021 17:52:53 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C8064100034; Fri, 16 Apr 2021 17:52:52 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 92F7225D00B; Fri, 16 Apr 2021 17:52:52 +0200 (CEST) Received: from [10.211.14.227] (10.75.127.48) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 16 Apr 2021 17:52:18 +0200 Subject: Re: [Linux-stm32] [PATCH 03/13] ARM: dts: stm32: fix timer nodes on STM32 MCU to prevent warnings To: Alexandre Torgue CC: , , Marek Vasut , , Manivannan Sadhasivam , Marcin Sloniewski , Ahmad Fatoum , , , , Lee Jones , , References: <20210415101037.1465-1-alexandre.torgue@foss.st.com> <20210415101037.1465-4-alexandre.torgue@foss.st.com> From: Fabrice Gasnier Message-ID: Date: Fri, 16 Apr 2021 17:52:17 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210415101037.1465-4-alexandre.torgue@foss.st.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG1NODE2.st.com (10.75.127.2) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-04-16_08:2021-04-16,2021-04-16 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/15/21 12:10 PM, Alexandre Torgue wrote: > Prevent warning seen with "make dtbs_check W=1" command: > > Warning (avoid_unnecessary_addr_size): /soc/timers@40001c00: unnecessary > address-cells/size-cells without "ranges" or child "reg" property > > Signed-off-by: Alexandre Torgue Hi Alexandre, Reviewed-by: Fabrice Gasnier Thanks, Fabrice > > diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi > index 41e0087bdbf9..8748d5850298 100644 > --- a/arch/arm/boot/dts/stm32f429.dtsi > +++ b/arch/arm/boot/dts/stm32f429.dtsi > @@ -283,8 +283,6 @@ > }; > > timers13: timers@40001c00 { > - #address-cells = <1>; > - #size-cells = <0>; > compatible = "st,stm32-timers"; > reg = <0x40001C00 0x400>; > clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; > @@ -299,8 +297,6 @@ > }; > > timers14: timers@40002000 { > - #address-cells = <1>; > - #size-cells = <0>; > compatible = "st,stm32-timers"; > reg = <0x40002000 0x400>; > clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; > @@ -633,8 +629,6 @@ > }; > > timers10: timers@40014400 { > - #address-cells = <1>; > - #size-cells = <0>; > compatible = "st,stm32-timers"; > reg = <0x40014400 0x400>; > clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; > @@ -649,8 +643,6 @@ > }; > > timers11: timers@40014800 { > - #address-cells = <1>; > - #size-cells = <0>; > compatible = "st,stm32-timers"; > reg = <0x40014800 0x400>; > clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; > diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi > index e1df603fc981..72c1b76684b6 100644 > --- a/arch/arm/boot/dts/stm32f746.dtsi > +++ b/arch/arm/boot/dts/stm32f746.dtsi > @@ -265,8 +265,6 @@ > }; > > timers13: timers@40001c00 { > - #address-cells = <1>; > - #size-cells = <0>; > compatible = "st,stm32-timers"; > reg = <0x40001C00 0x400>; > clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; > @@ -281,8 +279,6 @@ > }; > > timers14: timers@40002000 { > - #address-cells = <1>; > - #size-cells = <0>; > compatible = "st,stm32-timers"; > reg = <0x40002000 0x400>; > clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; > @@ -531,8 +527,6 @@ > }; > > timers10: timers@40014400 { > - #address-cells = <1>; > - #size-cells = <0>; > compatible = "st,stm32-timers"; > reg = <0x40014400 0x400>; > clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; > @@ -547,8 +541,6 @@ > }; > > timers11: timers@40014800 { > - #address-cells = <1>; > - #size-cells = <0>; > compatible = "st,stm32-timers"; > reg = <0x40014800 0x400>; > clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; > diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi > index 05ecdf9ff03a..6e42ca2dada2 100644 > --- a/arch/arm/boot/dts/stm32h743.dtsi > +++ b/arch/arm/boot/dts/stm32h743.dtsi > @@ -485,8 +485,6 @@ > }; > > lptimer4: timer@58002c00 { > - #address-cells = <1>; > - #size-cells = <0>; > compatible = "st,stm32-lptimer"; > reg = <0x58002c00 0x400>; > clocks = <&rcc LPTIM4_CK>; > @@ -501,8 +499,6 @@ > }; > > lptimer5: timer@58003000 { > - #address-cells = <1>; > - #size-cells = <0>; > compatible = "st,stm32-lptimer"; > reg = <0x58003000 0x400>; > clocks = <&rcc LPTIM5_CK>; >