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[23.128.96.18]) by mx.google.com with ESMTP id a25si5524959ejv.555.2021.04.16.15.11.23; Fri, 16 Apr 2021 15:11:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=HucNkTC4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235745AbhDPWES (ORCPT + 99 others); Fri, 16 Apr 2021 18:04:18 -0400 Received: from mail.kernel.org ([198.145.29.99]:42000 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234898AbhDPWES (ORCPT ); Fri, 16 Apr 2021 18:04:18 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id BEACE613D0 for ; Fri, 16 Apr 2021 22:03:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1618610632; bh=V8DN3hA4Oxq1kvmrAX7ZmoV2tbwog9YlXYaeOBmIKgY=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=HucNkTC4IYW+viOqXZffpGTIyfXgdQa+UuKbad+w4ncadyMdVsbVGLKXLEipniMf5 etxshN89bxyBFho6ljk2V7FFFKsHhO0zQf+frtXp5C7zKW5SeXtj0qF56uyXPdNj9R xTF73Ek3i0GV9wojbCabzh4Emk/CfidKTsrMd9j7yteOgT2zeFnifz0MWd2oBlC+ud G+QAl7x0ppszlljcY4ODuHUPvjB/Pfkv+G9e6SiDatD5OtTHYSB8et8mDfzK+PraJJ HpDaF9S0kZ5AgXEaFBlHInl2D97PTWgjweh4kZXFSic6x5Rn42CS9xQzrKal4Y9W+z yGDQhT/XTEIgQ== Received: by mail-ed1-f47.google.com with SMTP id z1so33985694edb.8 for ; Fri, 16 Apr 2021 15:03:52 -0700 (PDT) X-Gm-Message-State: AOAM533ukeMsTEB9qv3sQzl1u3yYySxZe1Ik/lGP9l8m/A3QMENmCY59 qr7ld4odkQalPhIAjditk+s9uU55y3R1TroU0wNuOA== X-Received: by 2002:aa7:d7d1:: with SMTP id e17mr12745493eds.84.1618610631260; Fri, 16 Apr 2021 15:03:51 -0700 (PDT) MIME-Version: 1.0 References: <87lf9nk2ku.fsf@oldenburg.str.redhat.com> In-Reply-To: From: Andy Lutomirski Date: Fri, 16 Apr 2021 15:03:39 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: Candidate Linux ABI for Intel AMX and hypothetical new related features To: Len Brown Cc: Andy Lutomirski , Willy Tarreau , Florian Weimer , "Bae, Chang Seok" , Dave Hansen , X86 ML , LKML , linux-abi@vger.kernel.org, "libc-alpha@sourceware.org" , Rich Felker , Kyle Huey , Keno Fischer Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 16, 2021 at 2:54 PM Len Brown wrote: > > On Thu, Apr 15, 2021 at 12:24 PM Andy Lutomirski wrote: > > On Wed, Apr 14, 2021 at 2:48 PM Len Brown wrote: > > > > > ... the transition penalty into and out of AMX code > > The concept of 'transition' exists between AVX and SSE instructions > because it is possible to mix both instruction sets and touch different > parts of the same registers. The "unused" parts of those registers > need to be tracked to assure that data is not lost when mixing. I get it. That does not explain why LDMXCSR and VLDMXCSR cause pipelines stalls. > > This concept is moot with AMX, which has its own dedicated registers. > > > What is the actual impact of a trivial function that initializes the > > tile config, does one tiny math op, and then does TILERELEASE? ^^^^ "does one tiny math op" AVX-512 *also* has sort-of-dedicated registers: ZMM16 and up. I still can't find any conclusive evidence as to whether that avoids the performance hit. Intel's track record at actually explaining what operations cause what particular performance disasters is poor, and your explanation is not helping the situation. Sorry.