Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
IronPort-SDR: HgHwxLmavdS4hymMN/PG9SPVCaBF01QIbNKGKVCH5xbfZpehW4YQB/FmcnlrJr8pf5Uulh09sD
 GjGsdTtXdPr4j0OlvUsTKe8BNl+X9YvfqEC0J9KdVQdpSGfZUg3qCQ8owynIL5Rwxxh7r97x+9
 OUUXIXUhypMv7iLcPgYF0lGiIRr8ENrHqvzu7uP6NIy/NbmqAVU1bdLOtVIK7divROGUbS1PEx
 td5f8iVy9mIKTBIfrux1l1VVClnql6TQj39qSPjrlFwW4k/dwqptlRADtTJuMoy8IS1C0IQRyE
 Cbc=
IronPort-SDR: s5VEf+h1tfIFhADcOGlYrMya5ufLkqficZSZ8qLi9+b55AjvelViMaegxOOhuSEjQmfMAsEi28
 lo4esMpChsNhHnKkh6v6PDzxAj7v5ILDqbXA/HmZiFliuE6lS4gI2/PQG6PwP7xWKc/FJ3ur0K
 wb4Q3YTo+c65dKnkkkuwzDGr8sYGYavro12yuWfH4W+B8D7JRxHkq56MF7x+XzRhbV7Re8GFfl
 AqS8tZLhNuBc8I5u2ZnKwlWIGnI8hMbb3wOfvABDhl4snBvqJe7poFfSy0p3trPb+0vROAu3+h
 2v68HjEPzyBImYTmZDNuqtF2
IronPort-SDR: 6uvZh02vxWp+6R7jRXQrNcr8pbxoVEP+QIOLZ/0/tAi7DzZrPR+LWngIYjHlEiJ67yrKYbgWUH
 keoSm6+JGA3gybd/dLs/TnUYpdAnEabcd6stPVgmdeJ+AiHTVHIX0hASUlzJaCkEd2ihgu6LC5
 opzMvL+xRCgDyYrf+u5n7k9pPVQJ2uD6MzrGsR/UJw1EH5tFWShf+jWNIMdODmE+bUtMDX4HpL
 HULceDUWv59gt1RLuBxdrC8TOFCEscKWI9gPUX1d4u+2prNHD+5NOHS+bxfLbTcMPEwy9/ODUu
 fW0=
WDCIronportException: Internal
From:   Avri Altman <avri.altman@wdc.com>
To:     Ulf Hansson <ulf.hansson@linaro.org>, linux-mmc@vger.kernel.org,
        Adrian Hunter <adrian.hunter@intel.com>
Cc:     linux-kernel@vger.kernel.org, Avri Altman <avri.altman@wdc.com>
Subject: [PATCH v2 2/2] mmc: block: Update ext_csd.cache_ctrl if it was written
Date:   Sun, 18 Apr 2021 08:59:53 +0300
Message-Id: <20210418055953.26959-3-avri.altman@wdc.com>
In-Reply-To: <20210418055953.26959-1-avri.altman@wdc.com>
References: <20210418055953.26959-1-avri.altman@wdc.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

The cache function can be turned ON and OFF by writing to the CACHE_CTRL
byte (EXT_CSD byte [33]).  However,  card->ext_csd.cache_ctrl is only
set on init if cache size > 0.

Fix that by explicitly setting ext_csd.cache_ctrl on ext-csd write.

Signed-off-by: Avri Altman <avri.altman@wdc.com>
---
 drivers/mmc/core/block.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c
index 6800feb70c92..0372702231ce 100644
--- a/drivers/mmc/core/block.c
+++ b/drivers/mmc/core/block.c
@@ -572,6 +572,18 @@ static int __mmc_blk_ioctl_cmd(struct mmc_card *card, struct mmc_blk_data *md,
 		main_md->part_curr = value & EXT_CSD_PART_CONFIG_ACC_MASK;
 	}
 
+	/*
+	 * Make sure to update CACHE_CTRL in case it was changed. The cache
+	 * will get turned back on if the card is re-initialized, e.g.
+	 * suspend/resume or hw reset in recovery.
+	 */
+	if ((MMC_EXTRACT_INDEX_FROM_ARG(cmd.arg) == EXT_CSD_CACHE_CTRL) &&
+	    (cmd.opcode == MMC_SWITCH)) {
+		u8 value = MMC_EXTRACT_VALUE_FROM_ARG(cmd.arg) & 1;
+
+		card->ext_csd.cache_ctrl = value;
+	}
+
 	/*
 	 * According to the SD specs, some commands require a delay after
 	 * issuing the command.
-- 
2.25.1