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[23.128.96.18]) by mx.google.com with ESMTP id d7si11941104edx.4.2021.04.19.03.25.35; Mon, 19 Apr 2021 03:25:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=M6O8dgdS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238827AbhDSJke (ORCPT + 99 others); Mon, 19 Apr 2021 05:40:34 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:28328 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S238734AbhDSJkA (ORCPT ); Mon, 19 Apr 2021 05:40:00 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13J9RIPj027858; Mon, 19 Apr 2021 11:39:13 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=selector1; bh=HcKt8Vhz/HkUFi+h7CXhtAU23HKbdmLcnuJLlezyb0M=; b=M6O8dgdSEwOE+GF1FUlclSuo5sRv4NTHJesDPh89Qtry4i72xqr/2xTsge32tvrmjbDF cTnviZ+GGW5NdBnoLBKZa0pC4exjskjWhR7aHdJWSCPrDbmmYofHzgnW1fgdroHcJ9oR Chs8NgSlPwggfw+UrSN8PI4E76y34SkGZirqoYhRJATOgQXGBNvEP9S74ULvybymPG9H AttMEx00H3bJW0vpbOLdG2cPvZaNYvzEc6ODpXL4ddGfD0++5CVwNcS/LZzD2Evc0fYQ JVb6E7neX0nOwiklE5SD9wkIflDl65l1nA7yA63aoL+n+M4+RTQR3Gz/NGQi4pKxWinL Ow== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 380s8c3bh0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 19 Apr 2021 11:39:13 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 250EE10002A; Mon, 19 Apr 2021 11:39:13 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1418220A07F; Mon, 19 Apr 2021 11:39:13 +0200 (CEST) Received: from localhost (10.75.127.51) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 19 Apr 2021 11:39:12 +0200 From: To: Michael Turquette , Stephen Boyd , Rob Herring , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Etienne Carriere , Gabriel Fernandez , CC: , , , , , Arnaud Pouliquen Subject: [PATCH v3 09/11] dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15 Date: Mon, 19 Apr 2021 11:38:50 +0200 Message-ID: <20210419093852.14978-10-gabriel.fernandez@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210419093852.14978-1-gabriel.fernandez@foss.st.com> References: <20210419093852.14978-1-gabriel.fernandez@foss.st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-04-19_05:2021-04-16,2021-04-19 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Gabriel Fernandez Add ID to SCMI0 to exposes reset controller for the MCU HOLD BOOT resource. Signed-off-by: Arnaud Pouliquen Signed-off-by: Gabriel Fernandez Acked-by: Rob Herring --- include/dt-bindings/reset/stm32mp1-resets.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index bc71924faa54..f3a0ed317835 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -7,6 +7,7 @@ #ifndef _DT_BINDINGS_STM32MP1_RESET_H_ #define _DT_BINDINGS_STM32MP1_RESET_H_ +#define MCU_HOLD_BOOT_R 2144 #define LTDC_R 3072 #define DSI_R 3076 #define DDRPERFM_R 3080 @@ -117,5 +118,6 @@ #define RST_SCMI0_RNG1 8 #define RST_SCMI0_MDMA 9 #define RST_SCMI0_MCU 10 +#define RST_SCMI0_MCU_HOLD_BOOT 11 #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ -- 2.17.1