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[23.128.96.18]) by mx.google.com with ESMTP id r15si21284735pgv.80.2021.04.20.01.25.13; Tue, 20 Apr 2021 01:25:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230346AbhDTIYN (ORCPT + 99 others); Tue, 20 Apr 2021 04:24:13 -0400 Received: from mail.kernel.org ([198.145.29.99]:45582 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229559AbhDTIYN (ORCPT ); Tue, 20 Apr 2021 04:24:13 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 21AFC61104; Tue, 20 Apr 2021 08:23:42 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lYlfX-008RtE-Pc; Tue, 20 Apr 2021 09:23:40 +0100 Date: Tue, 20 Apr 2021 09:23:29 +0100 Message-ID: <87h7k1qs8u.wl-maz@kernel.org> From: Marc Zyngier To: Robert Hancock Cc: tglx@linutronix.de, michal.simek@xilinx.com, linux-kernel@vger.kernel.org, anirudh@xilinx.com Subject: Re: [PATCH v2] irqchip/xilinx: Expose Kconfig option for Zynq/ZynqMP In-Reply-To: <20210419194245.210550-1-robert.hancock@calian.com> References: <20210419194245.210550-1-robert.hancock@calian.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: robert.hancock@calian.com, tglx@linutronix.de, michal.simek@xilinx.com, linux-kernel@vger.kernel.org, anirudh@xilinx.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 19 Apr 2021 20:42:45 +0100, Robert Hancock wrote: > > Previously the XILINX_INTC config option was hidden and only > auto-selected on the MicroBlaze platform. However, this IP can also be > used on the Zynq and ZynqMP platforms as a secondary cascaded > controller. Allow this option to be user-enabled on those platforms. > > Signed-off-by: Robert Hancock > --- > drivers/irqchip/Kconfig | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > index 15536e321df5..1020cc5a7800 100644 > --- a/drivers/irqchip/Kconfig > +++ b/drivers/irqchip/Kconfig > @@ -279,8 +279,13 @@ config XTENSA_MX > select GENERIC_IRQ_EFFECTIVE_AFF_MASK > > config XILINX_INTC > - bool > + bool "Xilinx Interrupt Controller IP" > + depends on MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || COMPILE_TEST Please drop COMPILE_TEST. As reported by the kernel test bot, there are architectures it can't be compiled on. M. -- Without deviation from the norm, progress is not possible.