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From:   Nava kishore Manne <navam@xilinx.com>
To:     Greg KH <gregkh@linuxfoundation.org>
CC:     "robh+dt@kernel.org" <robh+dt@kernel.org>,
        Michal Simek <michals@xilinx.com>,
        Derek Kiernan <dkiernan@xilinx.com>,
        Dragan Cvetic <draganc@xilinx.com>,
        "arnd@arndb.de" <arnd@arndb.de>, Rajan Vaja <RAJANV@xilinx.com>,
        Jolly Shah <JOLLYS@xilinx.com>,
        Tejas Patel <tejasp@xlnx.xilinx.com>,
        Amit Sunil Dhamne <amitsuni@xilinx.com>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "chinnikishore369@gmail.com" <chinnikishore369@gmail.com>,
        git <git@xilinx.com>
Subject: RE: [PATCH 5/5] misc: zynqmp: Add afi config driver
Thread-Topic: [PATCH 5/5] misc: zynqmp: Add afi config driver
Thread-Index: AQHXNb4YA+92oo6dgkaPdwzLOSQ8W6q9GRYAgABSSTA=
Date:   Tue, 20 Apr 2021 13:47:17 +0000
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References: <20210420081153.17020-1-nava.manne@xilinx.com>
 <20210420081153.17020-6-nava.manne@xilinx.com> <YH6V9Im3L/gJJ/CP@kroah.com>
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Hi Greg,

	Please find my response inline.

> -----Original Message-----
> From: Greg KH <gregkh@linuxfoundation.org>
> Sent: Tuesday, April 20, 2021 2:21 PM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: robh+dt@kernel.org; Michal Simek <michals@xilinx.com>; Derek Kiernan
> <dkiernan@xilinx.com>; Dragan Cvetic <draganc@xilinx.com>;
> arnd@arndb.de; Rajan Vaja <RAJANV@xilinx.com>; Jolly Shah
> <JOLLYS@xilinx.com>; Tejas Patel <tejasp@xlnx.xilinx.com>; Amit Sunil
> Dhamne <amitsuni@xilinx.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> chinnikishore369@gmail.com; git <git@xilinx.com>
> Subject: Re: [PATCH 5/5] misc: zynqmp: Add afi config driver
>=20
> On Tue, Apr 20, 2021 at 01:41:53PM +0530, Nava kishore Manne wrote:
> > This patch adds zynqmp afi config driver.This is useful for the
> > configuration of the PS-PL interface on Zynq US+ MPSoC platform.
> >
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > ---
> >  drivers/misc/Kconfig      | 11 ++++++
> >  drivers/misc/Makefile     |  1 +
> >  drivers/misc/zynqmp-afi.c | 83
> > +++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 95 insertions(+)
> >  create mode 100644 drivers/misc/zynqmp-afi.c
> >
> > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> > 877b43b3377d..d1ea1eeb3ac1 100644
> > --- a/drivers/misc/Kconfig
> > +++ b/drivers/misc/Kconfig
> > @@ -456,6 +456,17 @@ config ZYNQ_AFI
> >  	  between PS and PL, the AXI port data path should be configured
> >  	  with the proper Bus-width values
> >
> > +config ZYNQMP_AFI
> > +        tristate "Xilinx ZYNQMP AFI support"
> > +        help
> > +	  ZynqMP AFI driver support for writing to the AFI registers for
> > +	  configuring PS_PL Bus-width. Xilinx Zynq US+ MPSoC connect the
> > +	  PS to the programmable logic (PL) through the AXI port. This AXI
> > +	  port helps to establish the data path between the PS and PL.
> > +	  In-order to establish the proper communication path between
> > +	  PS and PL, the AXI port data path should be configured with
> > +	  the proper Bus-width values
> > +
> >  source "drivers/misc/c2port/Kconfig"
> >  source "drivers/misc/eeprom/Kconfig"
> >  source "drivers/misc/cb710/Kconfig"
> > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> > e9b03843100f..54bd0edc511e 100644
> > --- a/drivers/misc/Makefile
> > +++ b/drivers/misc/Makefile
> > @@ -57,3 +57,4 @@ obj-$(CONFIG_UACCE)		+=3D uacce/
> >  obj-$(CONFIG_XILINX_SDFEC)	+=3D xilinx_sdfec.o
> >  obj-$(CONFIG_HISI_HIKEY_USB)	+=3D hisi_hikey_usb.o
> >  obj-$(CONFIG_ZYNQ_AFI)		+=3D zynq-afi.o
> > +obj-$(CONFIG_ZYNQMP_AFI)	+=3D zynqmp-afi.o
> > diff --git a/drivers/misc/zynqmp-afi.c b/drivers/misc/zynqmp-afi.c new
> > file mode 100644 index 000000000000..a318652576d2
> > --- /dev/null
> > +++ b/drivers/misc/zynqmp-afi.c
> > @@ -0,0 +1,83 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Xilinx FPGA AFI bridge.
> > + * Copyright (c) 2018-2021 Xilinx Inc.
> > + */
> > +
> > +#include <linux/err.h>
> > +#include <linux/firmware/xlnx-zynqmp.h> #include <linux/io.h>
> > +#include <linux/module.h> #include <linux/of.h> #include
> > +<linux/platform_device.h> #include <linux/slab.h>
> > +
> > +/**
> > + * struct zynqmp_afi_fpga - AFI register description
> > + * @value: value to be written to the register
> > + * @regid: Register id for the register to be written
> > + */
> > +struct zynqmp_afi_fpga {
> > +	u32 value;
> > +	u32 regid;
> > +};
> > +
> > +static int zynqmp_afi_fpga_probe(struct platform_device *pdev)
> > +{
> > +	struct zynqmp_afi_fpga *zynqmp_afi_fpga;
> > +	struct device_node *np =3D pdev->dev.of_node;
> > +	int i, entries, ret;
> > +	u32 reg, val;
> > +
> > +	zynqmp_afi_fpga =3D devm_kzalloc(&pdev->dev,
> > +				       sizeof(*zynqmp_afi_fpga), GFP_KERNEL);
> > +	if (!zynqmp_afi_fpga)
> > +		return -ENOMEM;
> > +	platform_set_drvdata(pdev, zynqmp_afi_fpga);
> > +
> > +	entries =3D of_property_count_u32_elems(np, "config-afi");
> > +	if (!entries || (entries % 2)) {
> > +		dev_err(&pdev->dev, "Invalid number of registers\n");
> > +		return -EINVAL;
> > +	}
> > +
> > +	for (i =3D 0; i < entries / 2; i++) {
> > +		ret =3D of_property_read_u32_index(np, "config-afi", i * 2,
> &reg);
> > +		if (ret) {
> > +			dev_err(&pdev->dev, "failed to read register\n");
> > +			return -EINVAL;
> > +		}
> > +		ret =3D of_property_read_u32_index(np, "config-afi", i * 2 + 1,
> > +						 &val);
> > +		if (ret) {
> > +			dev_err(&pdev->dev, "failed to read value\n");
> > +			return -EINVAL;
> > +		}
> > +		ret =3D zynqmp_pm_afi(reg, val);
> > +		if (ret < 0) {
> > +			dev_err(&pdev->dev, "AFI register write error %d\n",
> > +				ret);
> > +			return ret;
> > +		}
> > +	}
> > +	return 0;
> > +}
>=20
> Again, why does this have to be in the kernel?  All it does is make a
> single call to the hardware based on some values read from the device
> tree.  Can't you do this from userspace?
>=20
For every PL design has its own PS-PL configuration.
This driver will be used by the overlay framework for configuring the inter=
face after programming the FPGA and before probing the drivers that are pre=
sent in the PL.

Regards,
Navakishore.