Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Subject: Re: [PATCH v11 2/4] arm64: dts: mt8183: Add node for the Mali GPU
To:     Nicolas Boichat <drinkcat@chromium.org>,
        Rob Herring <robh@kernel.org>,
        Steven Price <steven.price@arm.com>,
        Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc:     devicetree@vger.kernel.org,
        Tomeu Vizoso <tomeu.vizoso@collabora.com>, fshao@chromium.org,
        linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
        boris.brezillon@collabora.com, linux-mediatek@lists.infradead.org,
        hsinyi@chromium.org, Matthias Brugger <matthias.bgg@gmail.com>,
        hoegsberg@chromium.org, linux-arm-kernel@lists.infradead.org
References: <20210126011759.1605641-1-drinkcat@chromium.org>
 <20210126091747.v11.2.I9f45f5c1f975422d58b5904d11546349e9ccdc94@changeid>
From:   Neil Armstrong <narmstrong@baylibre.com>
Organization: Baylibre
Message-ID: <1a37f9be-8ec8-893a-e2fc-f0739948f71f@baylibre.com>
Date:   Tue, 20 Apr 2021 17:33:52 +0200
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101
 Thunderbird/78.7.1
MIME-Version: 1.0
In-Reply-To: <20210126091747.v11.2.I9f45f5c1f975422d58b5904d11546349e9ccdc94@changeid>
Content-Type: text/plain; charset=utf-8
Content-Language: en-US
Content-Transfer-Encoding: 7bit
Precedence: bulk

On 26/01/2021 02:17, Nicolas Boichat wrote:
> Add a basic GPU node for mt8183.
> 
> Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
> ---
> The binding we use with out-of-tree Mali drivers includes more
> clocks, this is used for devfreq: the out-of-tree driver switches
> clk_mux to clk_sub_parent (26Mhz), adjusts clk_main_parent, then
> switches clk_mux back to clk_main_parent:
> (see https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_runtime_pm.c#423)
> clocks =
>         <&topckgen CLK_TOP_MFGPLL_CK>,
>         <&topckgen CLK_TOP_MUX_MFG>,
>         <&clk26m>,
>         <&mfgcfg CLK_MFG_BG3D>;
> clock-names =
>         "clk_main_parent",
>         "clk_mux",
>         "clk_sub_parent",
>         "subsys_mfg_cg";
> (based on discussions, this probably belongs in the clock core)
> 
> This only matters for devfreq, that is disabled anyway as we don't
> have platform-specific code to handle >1 supplies.
> 
> Changes in v11:
>  - mt8183*.dts: remove incorrect supply-names
> 
> Changes in v10: None
> Changes in v9: None
> Changes in v8: None
> Changes in v7: None
> Changes in v6:
>  - Add gpu regulators to kukui dtsi as well.
>  - Power domains are now attached to spm, not scpsys
>  - Drop R-B.
> 
> Changes in v5:
>  - Rename "2d" power domain to "core2" (keep R-B again).
> 
> Changes in v4:
>  - Add power-domain-names to describe the 3 domains.
>    (kept Alyssa's reviewed-by as the change is minor)
> 
> Changes in v3: None
> Changes in v2:
>  - Use sram instead of mali_sram as SRAM supply name.
>  - Rename mali@ to gpu@.
> 
>  arch/arm64/boot/dts/mediatek/mt8183-evb.dts   |   5 +
>  .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi |   5 +
>  arch/arm64/boot/dts/mediatek/mt8183.dtsi      | 105 ++++++++++++++++++
>  3 files changed, 115 insertions(+)
> 

If you re-spin, you can also add the same changes to mt8183-pumpkin.dts :
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
index eb6e595c2975..cc23e5df391e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
@@ -68,6 +68,11 @@ &auxadc {
        status = "okay";
 };

+&gpu {
+       mali-supply = <&mt6358_vgpu_reg>;
+       sram-supply = <&mt6358_vsram_gpu_reg>;
+};
+
 &i2c0 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2c_pins_0>;

I did a boot-test of the platform with panfrost and drm-misc-next and it worked fine.

Thanks,
Neil

> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> index cba2d8933e79..1cfbea5a0101 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> @@ -42,6 +42,11 @@ &auxadc {
>  	status = "okay";
>  };
>  
> +&gpu {
> +	mali-supply = <&mt6358_vgpu_reg>;
> +	sram-supply = <&mt6358_vsram_gpu_reg>;
> +};
> +
>  &i2c0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&i2c_pins_0>;
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> index bf2ad1294dd3..a38315b604df 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> @@ -249,6 +249,11 @@ &cpu7 {
>  	proc-supply = <&mt6358_vproc11_reg>;
>  };
>  
> +&gpu {
> +	mali-supply = <&mt6358_vgpu_reg>;
> +	sram-supply = <&mt6358_vsram_gpu_reg>;
> +};
> +
>  &i2c0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&i2c0_pins>;
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 5b782a4769e7..5430e05e18a0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -964,6 +964,111 @@ mfgcfg: syscon@13000000 {
>  			#clock-cells = <1>;
>  		};
>  
> +		gpu: gpu@13040000 {
> +			compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
> +			reg = <0 0x13040000 0 0x4000>;
> +			interrupts =
> +				<GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>,
> +				<GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>,
> +				<GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
> +			interrupt-names = "job", "mmu", "gpu";
> +
> +			clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
> +
> +			power-domains =
> +				<&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
> +				<&spm MT8183_POWER_DOMAIN_MFG_CORE1>,
> +				<&spm MT8183_POWER_DOMAIN_MFG_2D>;
> +			power-domain-names = "core0", "core1", "core2";
> +
> +			operating-points-v2 = <&gpu_opp_table>;
> +		};
> +
> +		gpu_opp_table: opp_table0 {
> +			compatible = "operating-points-v2";
> +			opp-shared;
> +
> +			opp-300000000 {
> +				opp-hz = /bits/ 64 <300000000>;
> +				opp-microvolt = <625000>, <850000>;
> +			};
> +
> +			opp-320000000 {
> +				opp-hz = /bits/ 64 <320000000>;
> +				opp-microvolt = <631250>, <850000>;
> +			};
> +
> +			opp-340000000 {
> +				opp-hz = /bits/ 64 <340000000>;
> +				opp-microvolt = <637500>, <850000>;
> +			};
> +
> +			opp-360000000 {
> +				opp-hz = /bits/ 64 <360000000>;
> +				opp-microvolt = <643750>, <850000>;
> +			};
> +
> +			opp-380000000 {
> +				opp-hz = /bits/ 64 <380000000>;
> +				opp-microvolt = <650000>, <850000>;
> +			};
> +
> +			opp-400000000 {
> +				opp-hz = /bits/ 64 <400000000>;
> +				opp-microvolt = <656250>, <850000>;
> +			};
> +
> +			opp-420000000 {
> +				opp-hz = /bits/ 64 <420000000>;
> +				opp-microvolt = <662500>, <850000>;
> +			};
> +
> +			opp-460000000 {
> +				opp-hz = /bits/ 64 <460000000>;
> +				opp-microvolt = <675000>, <850000>;
> +			};
> +
> +			opp-500000000 {
> +				opp-hz = /bits/ 64 <500000000>;
> +				opp-microvolt = <687500>, <850000>;
> +			};
> +
> +			opp-540000000 {
> +				opp-hz = /bits/ 64 <540000000>;
> +				opp-microvolt = <700000>, <850000>;
> +			};
> +
> +			opp-580000000 {
> +				opp-hz = /bits/ 64 <580000000>;
> +				opp-microvolt = <712500>, <850000>;
> +			};
> +
> +			opp-620000000 {
> +				opp-hz = /bits/ 64 <620000000>;
> +				opp-microvolt = <725000>, <850000>;
> +			};
> +
> +			opp-653000000 {
> +				opp-hz = /bits/ 64 <653000000>;
> +				opp-microvolt = <743750>, <850000>;
> +			};
> +
> +			opp-698000000 {
> +				opp-hz = /bits/ 64 <698000000>;
> +				opp-microvolt = <768750>, <868750>;
> +			};
> +
> +			opp-743000000 {
> +				opp-hz = /bits/ 64 <743000000>;
> +				opp-microvolt = <793750>, <893750>;
> +			};
> +
> +			opp-800000000 {
> +				opp-hz = /bits/ 64 <800000000>;
> +				opp-microvolt = <825000>, <925000>;
> +			};
> +		};
> +
>  		mmsys: syscon@14000000 {
>  			compatible = "mediatek,mt8183-mmsys", "syscon";
>  			reg = <0 0x14000000 0 0x1000>;
>