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Date:   Tue, 20 Apr 2021 22:13:05 +0200
From:   Pavel Machek <pavel@ucw.cz>
To:     Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc:     linux-kernel@vger.kernel.org, stable@vger.kernel.org,
        Sanjay Kumar <sanjay.k.kumar@intel.com>,
        Dave Jiang <dave.jiang@intel.com>,
        Vinod Koul <vkoul@kernel.org>, Sasha Levin <sashal@kernel.org>
Subject: Re: [PATCH 5.11 007/122] dmaengine: idxd: Fix clobbering of SWERR
 overflow bit on writeback
Message-ID: <20210420201305.GA9942@duo.ucw.cz>
References: <20210419130530.166331793@linuxfoundation.org>
 <20210419130530.423797059@linuxfoundation.org>
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Hi!

> Current code blindly writes over the SWERR and the OVERFLOW bits. Write
> back the bits actually read instead so the driver avoids clobbering the
> OVERFLOW bit that comes after the register is read.

I believe this is incorrect. Changelog explains that we need to
preserve bits in the register...

> diff --git a/drivers/dma/idxd/irq.c b/drivers/dma/idxd/irq.c
> index a60ca11a5784..f1463fc58112 100644
> --- a/drivers/dma/idxd/irq.c
> +++ b/drivers/dma/idxd/irq.c
> @@ -124,7 +124,9 @@ static int process_misc_interrupts(struct idxd_device=
 *idxd, u32 cause)
>  		for (i =3D 0; i < 4; i++)
>  			idxd->sw_err.bits[i] =3D ioread64(idxd->reg_base +
>  					IDXD_SWERR_OFFSET + i * sizeof(u64));
> -		iowrite64(IDXD_SWERR_ACK, idxd->reg_base + IDXD_SWERR_OFFSET);
> +
> +		iowrite64(idxd->sw_err.bits[0] & IDXD_SWERR_ACK,
> +			  idxd->reg_base + IDXD_SWERR_OFFSET);

=2E..but that is not what the code does.

I suspect it should be=20

> +		iowrite64(idxd->sw_err.bits[0] | IDXD_SWERR_ACK,
> +			  idxd->reg_base + IDXD_SWERR_OFFSET);

Best regards,
								Pavel

--=20
http://www.livejournal.com/~pavelmachek

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