Received: by 2002:a05:6a10:a841:0:0:0:0 with SMTP id d1csp118257pxy; Wed, 21 Apr 2021 20:37:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzmoyYBB25cUC/YRqXuIcZOX/Rrik78A8LNtDLByvsXEuR534daTH7t99r3er25FiVV7/SN X-Received: by 2002:a17:906:4ed1:: with SMTP id i17mr1051473ejv.424.1619062670472; Wed, 21 Apr 2021 20:37:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619062670; cv=none; d=google.com; s=arc-20160816; b=FGlLcHMu4elnuRjr3DK0VQrMTnNu/K0ekjF3xUiPEF6AGeQUCfPU7D0jeqLvzHsoo6 K4PuB/ge8py3hiPU5c3Qh1P/RIgJvSTs0ffqJh8B6lJYHy/OmEsEN9ta/UOsHvWQTw+W 6B+BhjyiP1QLZ9LBOspIH5Q2jBB9tzjqfX6HTOtPJnd4eVXpPujvPANDrGwjCEe3S7sa OiXQTeXBkQGkLwk8xxZ4HXR2S/YyPyftmBAQcMi7cJfATlXNbZWL/Li6T7UQTdQ3mMK+ Y6YaSHlr81FFUx7L7/3USEvZ6rtliLW4IqgT7ln/kCUV1L7yNJou6ObNIlOrYPnXR7Rm MYBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=1wdpplQB7FRCEQJ6iK3dCmJBKChSU3ZVmSBYq8Yt3N8=; b=ficNpsqr9ofI2vWea3XV5GLo2aIASpmXBQYPUAlb/vX+GKVwAVgH54MaNC+ApqsRcL zwgvWkVEbfQ59Im9DY4bm529yq0yaijx9Lbc+QMoVQu4rq8gNa41vHTMPCANw8kyCT5w DYjb1fjSKvFLkUKEJ5Onw5WoQsZG8pTuJdLTN24V5yVRMGwpkPyqPRb278+cody75I6G 9ULSMd7mNhLg3klU86o8G6klq6pjfIznBHSuSaIyWghTOwPvuDjc/kIUQmt8vfevvqjL cJxy09luFukaO16PInIjNwUN6pmh30QoxU//CBR5W1BgzW6eA4Uop5Wvbe6xhmfQ33bN 0HMw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a17si1020327edx.275.2021.04.21.20.37.27; Wed, 21 Apr 2021 20:37:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234728AbhDVDgs (ORCPT + 99 others); Wed, 21 Apr 2021 23:36:48 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:48728 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234716AbhDVDgr (ORCPT ); Wed, 21 Apr 2021 23:36:47 -0400 X-UUID: 6c61a8f8a36f4d48b3aa977653ea8851-20210422 X-UUID: 6c61a8f8a36f4d48b3aa977653ea8851-20210422 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2146847449; Thu, 22 Apr 2021 11:36:09 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Apr 2021 11:36:07 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 22 Apr 2021 11:36:06 +0800 From: Zhiyong Tao To: , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH v5] pinctrl: add rsel setting on MT8195 Date: Thu, 22 Apr 2021 11:35:59 +0800 Message-ID: <20210422033559.29700-2-zhiyong.tao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210422033559.29700-1-zhiyong.tao@mediatek.com> References: <20210422033559.29700-1-zhiyong.tao@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 4751D653B100337B4670D9DA71444D5CC62E43A955A1B1D0D0D2B03C28ED45912000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch provides rsel setting on MT8195. Signed-off-by: Zhiyong Tao --- drivers/pinctrl/mediatek/pinctrl-mt8195.c | 22 +++++++++++++++++++ .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 14 ++++++++++++ .../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 10 +++++++++ drivers/pinctrl/mediatek/pinctrl-paris.c | 16 ++++++++++++++ 4 files changed, 62 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c index a7500e18bb1d..66608b8d346a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c @@ -779,6 +779,25 @@ static const struct mtk_pin_field_calc mt8195_pin_drv_adv_range[] = { PIN_FIELD_BASE(45, 45, 1, 0x040, 0x10, 9, 3), }; +static const struct mtk_pin_field_calc mt8195_pin_rsel_range[] = { + PIN_FIELD_BASE(8, 8, 4, 0x0c0, 0x10, 15, 3), + PIN_FIELD_BASE(9, 9, 4, 0x0c0, 0x10, 0, 3), + PIN_FIELD_BASE(10, 10, 4, 0x0c0, 0x10, 18, 3), + PIN_FIELD_BASE(11, 11, 4, 0x0c0, 0x10, 3, 3), + PIN_FIELD_BASE(12, 12, 4, 0x0c0, 0x10, 21, 3), + PIN_FIELD_BASE(13, 13, 4, 0x0c0, 0x10, 6, 3), + PIN_FIELD_BASE(14, 14, 4, 0x0c0, 0x10, 24, 3), + PIN_FIELD_BASE(15, 15, 4, 0x0c0, 0x10, 9, 3), + PIN_FIELD_BASE(16, 16, 4, 0x0c0, 0x10, 27, 3), + PIN_FIELD_BASE(17, 17, 4, 0x0c0, 0x10, 12, 3), + PIN_FIELD_BASE(29, 29, 2, 0x080, 0x10, 0, 3), + PIN_FIELD_BASE(30, 30, 2, 0x080, 0x10, 3, 3), + PIN_FIELD_BASE(34, 34, 1, 0x0e0, 0x10, 0, 3), + PIN_FIELD_BASE(35, 35, 1, 0x0e0, 0x10, 3, 3), + PIN_FIELD_BASE(44, 44, 1, 0x0e0, 0x10, 6, 3), + PIN_FIELD_BASE(45, 45, 1, 0x0e0, 0x10, 9, 3), +}; + static const struct mtk_pin_reg_calc mt8195_reg_cals[PINCTRL_PIN_REG_MAX] = { [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8195_pin_mode_range), [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8195_pin_dir_range), @@ -793,6 +812,7 @@ static const struct mtk_pin_reg_calc mt8195_reg_cals[PINCTRL_PIN_REG_MAX] = { [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8195_pin_r0_range), [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8195_pin_r1_range), [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8195_pin_drv_adv_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8195_pin_rsel_range), }; static const char * const mt8195_pinctrl_register_base_names[] = { @@ -823,6 +843,8 @@ static const struct mtk_pin_soc mt8195_data = { .drive_get = mtk_pinconf_drive_get_rev1, .adv_drive_get = mtk_pinconf_adv_drive_get_raw, .adv_drive_set = mtk_pinconf_adv_drive_set_raw, + .rsel_set = mtk_pinconf_rsel_set, + .rsel_get = mtk_pinconf_rsel_get, }; static const struct of_device_id mt8195_pinctrl_of_match[] = { diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 2b51f4a9b860..d1526d0c6248 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -1041,6 +1041,20 @@ int mtk_pinconf_adv_drive_get_raw(struct mtk_pinctrl *hw, } EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get_raw); +int mtk_pinconf_rsel_set(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 arg) +{ + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_RSEL, arg); +} +EXPORT_SYMBOL_GPL(mtk_pinconf_rsel_set); + +int mtk_pinconf_rsel_get(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 *val) +{ + return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_RSEL, val); +} +EXPORT_SYMBOL_GPL(mtk_pinconf_rsel_get); + MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Sean Wang "); MODULE_DESCRIPTION("Pin configuration library module for mediatek SoCs"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h index fd5ce9c5dcbd..570e8da7bf38 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h @@ -67,6 +67,7 @@ enum { PINCTRL_PIN_REG_DRV_E0, PINCTRL_PIN_REG_DRV_E1, PINCTRL_PIN_REG_DRV_ADV, + PINCTRL_PIN_REG_RSEL, PINCTRL_PIN_REG_MAX, }; @@ -237,6 +238,10 @@ struct mtk_pin_soc { const struct mtk_pin_desc *desc, u32 arg); int (*adv_drive_get)(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 *val); + int (*rsel_set)(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 arg); + int (*rsel_get)(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 *val); /* Specific driver data */ void *driver_data; @@ -320,5 +325,10 @@ int mtk_pinconf_adv_drive_set_raw(struct mtk_pinctrl *hw, int mtk_pinconf_adv_drive_get_raw(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 *val); +int mtk_pinconf_rsel_set(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 arg); +int mtk_pinconf_rsel_get(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 *val); + bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n); #endif /* __PINCTRL_MTK_COMMON_V2_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index da1f19288aa6..392fdfcb5b87 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -22,6 +22,8 @@ #define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3) #define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4) #define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5) +#define MTK_PIN_CONFIG_RSEL (PIN_CONFIG_END + 6) + static const struct pinconf_generic_params mtk_custom_bindings[] = { {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0}, @@ -29,6 +31,7 @@ static const struct pinconf_generic_params mtk_custom_bindings[] = { {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1}, {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1}, {"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2}, + {"mediatek,rsel", MTK_PIN_CONFIG_RSEL, 2}, }; #ifdef CONFIG_DEBUG_FS @@ -38,6 +41,7 @@ static const struct pin_config_item mtk_conf_items[] = { PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true), PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true), PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true), + PCONFDUMP(MTK_PIN_CONFIG_RSEL, "rsel", NULL, true), }; #endif @@ -176,6 +180,12 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, else err = -ENOTSUPP; break; + case MTK_PIN_CONFIG_RSEL: + if (hw->soc->rsel_get) + err = hw->soc->rsel_get(hw, desc, &ret); + else + err = -ENOTSUPP; + break; default: err = -ENOTSUPP; } @@ -295,6 +305,12 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, else err = -ENOTSUPP; break; + case MTK_PIN_CONFIG_RSEL: + if (hw->soc->rsel_set) + err = hw->soc->rsel_set(hw, desc, arg); + else + err = -ENOTSUPP; + break; default: err = -ENOTSUPP; } -- 2.18.0