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Date:   Thu, 22 Apr 2021 21:39:24 -0700 (PDT)
Subject:     Re: [PATCH] implement flush_cache_vmap for RISC-V
In-Reply-To: <18d198ac-7bc0-934d-e1e9-eca01b790d61@ghiti.fr>
CC:     Jisheng.Zhang@synaptics.com, liu@jiuyang.me,
        waterman@eecs.berkeley.edu,
        Paul Walmsley <paul.walmsley@sifive.com>,
        aou@eecs.berkeley.edu, akpm@linux-foundation.org,
        geert@linux-m68k.org, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org
From:   Palmer Dabbelt <palmer@dabbelt.com>
To:     alex@ghiti.fr
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On Wed, 14 Apr 2021 00:03:13 PDT (-0700), alex@ghiti.fr wrote:
> Hi,
>
> Le 4/12/21 à 3:08 AM, Jisheng Zhang a écrit :
>> Hi Jiuyang,
>>
>> On Mon, 12 Apr 2021 00:05:30 +0000 Jiuyang Liu <liu@jiuyang.me> wrote:
>>
>>
>>>
>>> This patch implements flush_cache_vmap for RISC-V, since it modifies PTE.
>>> Without this patch, SFENCE.VMA won't be added to related codes, which
>>> might introduce a bug in the out-of-order micro-architecture
>>> implementations.
>>>
>>> Signed-off-by: Jiuyang Liu <liu@jiuyang.me>
>>> Reviewed-by: Alexandre Ghiti <alex@ghiti.fr>
>>> Reviewed-by: Palmer Dabbelt <palmer@dabbelt.com>
>>
>> IIRC, Palmer hasn't given this Reviewed-by tag.

Yes.  In fact, I gave the opposite of a RB: we shouldn't have this, at 
least without some demonstration of a meaningful performance improvement 
and likely with a host of other changes to change the whole port over to 
avoid relying on traps to handle new mappings.  I really don't think 
that's a sane way to go, as the theory is that reasonable 
microarchitectures won't have big windows over which these faults can 
occur so there won't be that many of them.  If it ends up being an issue 
on real hardware we can try and sort something out, but it's going to be 
a lot of work as we'll need to avoid hurting performance on 
implementations that don't make invalid mappings visible often.

>>
>>> ---
>>
>> Could you plz add version and changes? IIRC, this is the v3.
>>
>>>   arch/riscv/include/asm/cacheflush.h | 6 ++++++
>>>   1 file changed, 6 insertions(+)
>>>
>>> diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
>>> index 23ff70350992..3fd528badc35 100644
>>> --- a/arch/riscv/include/asm/cacheflush.h
>>> +++ b/arch/riscv/include/asm/cacheflush.h
>>> @@ -30,6 +30,12 @@ static inline void flush_dcache_page(struct page *page)
>>>   #define flush_icache_user_page(vma, pg, addr, len) \
>>>          flush_icache_mm(vma->vm_mm, 0)
>>>
>>> +/*
>>> + * flush_cache_vmap is invoked after map_kernel_range() has installed the page
>>> + * table entries, which modifies PTE, SFENCE.VMA should be inserted.
>>
>> Just my humble opinion, flush_cache_vmap() may not be necessary. vmalloc_fault
>> can take care of this, and finally sfence.vma is inserted in related path.
>>
>
>
> I believe Palmer and Jisheng are right, my initial proposal to implement
> flush_cache_vmap is wrong.
>
> But then, Jiuyang should not have noticed any problem here, so what's
> wrong? @Jiuyang: Does implementing flush_cache_vmap fix your issue?
>
> And regarding flush_cache_vunmap, from Jisheng call stack, it seems also
> not necessary.

FWIW: I still think that flush_cache_vunmap() is necessary -- we don't 
have any other way to guarantee that mapping isn't visible.  Implementing 
flush_cache_vmap() could work around the real bug of lacking 
flush_cache_vunmap(), as we'd see stale mappings.

That said, it could just be covering up some other bug.  Wouldn't be 
surprised if it's a bug in our port, but this is the sort of thing that 
could also be a hardware bug of some sort.

>
> @Jiuyang: Can you tell us more about what you noticed?
>
>
>> Regards
>>
>>> + */
>>> +#define flush_cache_vmap(start, end) flush_tlb_all()
>>> +
>>>   #ifndef CONFIG_SMP
>>>
>>>   #define flush_icache_all() local_flush_icache_all()
>>> --
>>> 2.31.1
>>
>> _______________________________________________
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>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>>