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Subject: Re: [PATCH v2] KVM: SVM: Delay restoration of host MSR_TSC_AUX until
 return to userspace
To:     Sean Christopherson <seanjc@google.com>,
        Reiji Watanabe <reijiw@google.com>
Cc:     Vitaly Kuznetsov <vkuznets@redhat.com>,
        Wanpeng Li <wanpengli@tencent.com>,
        Jim Mattson <jmattson@google.com>,
        Joerg Roedel <joro@8bytes.org>, kvm@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Tom Lendacky <thomas.lendacky@amd.com>
References: <20210422001736.3255735-1-seanjc@google.com>
 <CAAeT=FxaRV+za7yk8_9p45k4ui3QJx90gN4b8k4egrxux=QWFA@mail.gmail.com>
 <YIHYsa1+psfnszcv@google.com>
From:   Paolo Bonzini <pbonzini@redhat.com>
Message-ID: <8cc2bb9a-167e-598c-6a9e-c23e943b1248@redhat.com>
Date:   Fri, 23 Apr 2021 08:13:11 +0200
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On 22/04/21 22:12, Sean Christopherson wrote:
> 	case MSR_TSC_AUX:
> 		if (!boot_cpu_has(X86_FEATURE_RDTSCP))
> 			return 1;
> 
> 		if (!msr_info->host_initiated &&
> 		    !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
> 			return 1;
> 
> 		/*
> 		 * TSC_AUX is usually changed only during boot and never read
> 		 * directly.  Intercept TSC_AUX instead of exposing it to the
> 		 * guest via direct_access_msrs, and switch it via user return.
> 		 */
> 		preempt_disable();
> 		r = kvm_set_user_return_msr(TSC_AUX_URET_SLOT, data, -1ull);
> 		preempt_enable();
> 		if (r)
> 			return 1;
> 
> 		/*
> 		 * Bits 63:32 are dropped by AMD CPUs, but are reserved on
> 		 * Intel CPUs.  AMD's APM has incomplete and conflicting info
> 		 * on the architectural behavior; emulate current hardware as
> 		 * doing so ensures migrating from AMD to Intel won't explode.
> 		 */
> 		svm->tsc_aux = (u32)data;
> 		break;
> 

Ok, squashed in the following:

diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 14ff7f0963e9..00e9680969a2 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -2875,16 +2875,28 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
  		if (!boot_cpu_has(X86_FEATURE_RDTSCP))
  			return 1;
  
+		if (!msr_info->host_initiated &&
+		    !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
+			return 1;
+
  		/*
  		 * TSC_AUX is usually changed only during boot and never read
  		 * directly.  Intercept TSC_AUX instead of exposing it to the
  		 * guest via direct_access_msrs, and switch it via user return.
  		 */
-		svm->tsc_aux = data;
-
  		preempt_disable();
-		kvm_set_user_return_msr(TSC_AUX_URET_SLOT, data, -1ull);
+		r = kvm_set_user_return_msr(TSC_AUX_URET_SLOT, data, -1ull);
  		preempt_enable();
+		if (r)
+			return 1;
+
+		/*
+		 * Bits 63:32 are dropped by AMD CPUs, but are reserved on
+		 * Intel CPUs.  AMD's APM has incomplete and conflicting info
+		 * on the architectural behavior; emulate current hardware as
+		 * doing so ensures migrating from AMD to Intel won't explode.
+		 */
+		svm->tsc_aux = (u32)data;
  		break;
  	case MSR_IA32_DEBUGCTLMSR:
  		if (!boot_cpu_has(X86_FEATURE_LBRV)) {

Paolo