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Date:   Fri, 23 Apr 2021 13:18:57 +0100
From:   Mark Brown <broonie@kernel.org>
To:     Jon Lin <jon.lin@rock-chips.com>
Cc:     heiko@sntech.de, linux-spi@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
        kernel@esmil.dk
Subject: Re: [PATCH v1 6/8] spi: rockchip: Set rx_fifo interrupt waterline
 base on transfer item
Message-ID: <20210423121857.GC5507@sirena.org.uk>
References: <20210423084155.17439-1-jon.lin@rock-chips.com>
 <20210423084750.18533-1-jon.lin@rock-chips.com>
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On Fri, Apr 23, 2021 at 04:47:48PM +0800, Jon Lin wrote:
> The error here is to calculate the width as 8 bits. In fact, 16 bits
> should be considered.

Bugfix patches like this should go at the start of a series so they can
be sent as fixes without any dependencies on earlier patches.

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