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[23.128.96.18]) by mx.google.com with ESMTP id o7si6421528ejj.449.2021.04.23.17.51.24; Fri, 23 Apr 2021 17:51:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20161025 header.b=lJHyP2rR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244559AbhDXAub (ORCPT + 99 others); Fri, 23 Apr 2021 20:50:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244354AbhDXAsg (ORCPT ); Fri, 23 Apr 2021 20:48:36 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1069C061359 for ; Fri, 23 Apr 2021 17:47:33 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id v3-20020a05690204c3b02904e65b70792dso26595303ybs.1 for ; Fri, 23 Apr 2021 17:47:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=1D0TlyZZx7JwVOxkgqn3lnDpgF3MCu1QmI2F6hIBoT4=; b=lJHyP2rRzUH35KcQlgXnydQwYs0SMuzctWrf1uue9kHOp9MJrRXHtC5IpS9bUmg5B/ A0Q62gvdYDqZ3MbhDcdCt2n4G9uugT2Ala6NsNZ1yR/8b9BTCNMSopmxcVmTV3mZHHz3 OH7EpGIBqx8kcnN9000YhwJa0v+t2TObsImK0uRlzEIfTDwY2yIk9O6ZUAQe5nsIbx7R bGKT2k5BRJPrbEGodj/Lr5M/gKBDBEwh75aq7eELmv0Dvl9UduuuCBtRyMAyBQiO4uiP Mr8AgekMCAryuK0bBxqiaQ+xyniOnc0wvV7dQNDLMIRyk9jEbrIABGpyQ3bBRtNXUcyE g8Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=1D0TlyZZx7JwVOxkgqn3lnDpgF3MCu1QmI2F6hIBoT4=; b=nxqVjCJuVmGbiGYjojkt+EPBkMxWuZrHgmVcecIZsXd5tZFWn/Dtn8aNIC93Lm/73m 76GkPd9yQip9D5eVqJm+luvV2sF5Y9yL/WlNPuPjBK89adwsz4782smpKM7kvJ0n+ImF D178oAgIn8D5VP1JBRU4srDTolMddbt9EgrdaCL9Ox5CQ27qDgM+1O9eMUulN3Du38Sh 2pFHz62t6GsNkgiRQWS/xOajEmsxmBPgKSHYJgXKFg8ECmZuywHS7T8vq6jimz+QLPN7 8i58t0/y4ubfMiuJL5326/3MEZ0eSNyLFfFsb6zOAYBNr21WRW8c8ZCizhT3TyFcBW/b kVDw== X-Gm-Message-State: AOAM533Y0tC+XGsT0Ul+OGBhjxEFQjQ8jlgFQqfAwnTZvwQkkmgutpk3 fwzTywB1pUGoQ74+ckq83CYVOrwSjik= X-Received: from seanjc798194.pdx.corp.google.com ([2620:15c:f:10:ad52:3246:e190:f070]) (user=seanjc job=sendgmr) by 2002:a25:2a16:: with SMTP id q22mr6068085ybq.379.1619225253134; Fri, 23 Apr 2021 17:47:33 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 23 Apr 2021 17:46:17 -0700 In-Reply-To: <20210424004645.3950558-1-seanjc@google.com> Message-Id: <20210424004645.3950558-16-seanjc@google.com> Mime-Version: 1.0 References: <20210424004645.3950558-1-seanjc@google.com> X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [PATCH 15/43] KVM: x86: Set BSP bit in reset BSP vCPU's APIC base by default From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Set the BSP bit appropriately during local APIC "reset" instead of relying on vendor code to clean up at a later point. This is a step towards consolidating the local APIC, VMX, and SVM xAPIC initialization code. Signed-off-by: Sean Christopherson --- arch/x86/kvm/lapic.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index c11f23753a5b..b088f6984b37 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2305,6 +2305,7 @@ EXPORT_SYMBOL_GPL(kvm_apic_update_apicv); void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) { struct kvm_lapic *apic = vcpu->arch.apic; + u64 msr_val; int i; if (!apic) @@ -2314,8 +2315,10 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) hrtimer_cancel(&apic->lapic_timer.timer); if (!init_event) { - kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE | - MSR_IA32_APICBASE_ENABLE); + msr_val = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE; + if (kvm_vcpu_is_reset_bsp(vcpu)) + msr_val |= MSR_IA32_APICBASE_BSP; + kvm_lapic_set_base(vcpu, msr_val); kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); } kvm_apic_set_version(apic->vcpu); -- 2.31.1.498.g6c1eba8ee3d-goog