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Subject: Re: [PATCH] MIPS:DTS:Correct device id and class code of pcie for
 Loongnon-2K
To:     Jiaxun Yang <jiaxun.yang@flygoat.com>,
        Rob Herring <robh+dt@kernel.org>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Qing Zhang <zhangqing@loongson.cn>
Cc:     devicetree@vger.kernel.org,
        "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
        linux-kernel@vger.kernel.org
References: <20210425052817.27373-1-maoxiaochuan@loongson.cn>
 <8cd60ba7-b0db-450f-8285-eb5429c4f3ec@www.fastmail.com>
From:   Xiaochuan Mao <maoxiaochuan@loongson.cn>
Message-ID: <60a86212-d0d4-7c3f-8ccd-20532fbf4b0c@loongson.cn>
Date:   Sun, 25 Apr 2021 20:05:44 +0800
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On 2021/4/25 下午6:39, Jiaxun Yang wrote:
>
> On Sun, Apr 25, 2021, at 1:28 PM, Xiaochuan Mao wrote:
>> from Loongson-2K user manual know that Loongson-2K have two
>> pcie controller pcie0 and pcie1, pcie0 have four port named port0~port3
>> and pcie1 have 2 port named port0~port1. the device id of port0 is 7a19
>> in each pcie controller and others are 7a09. and their class code is 0b0300.
> The manual is obviously incorrect.
>
> class0604 is PCI to PCI bridge that matches. hardware. 0b03 is undefined.
>
> Thanks.
thanks your suggest ,  is my mistake .
>> Signed-off-by: Xiaochuan Mao <maoxiaochuan@loongson.cn>
>> ---
>>  .../boot/dts/loongson/loongson64-2k1000.dtsi  | 40 +++++++++----------
>>  1 file changed, 20 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi 
>> b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
>> index 569e814def83..a95121359080 100644
>> --- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
>> +++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
>> @@ -150,8 +150,8 @@
>>  			pci_bridge@9,0 {
>>  				compatible = "pci0014,7a19.0",
>>  						   "pci0014,7a19",
>> -						   "pciclass060400",
>> -						   "pciclass0604";
>> +						   "pciclass0b0300",
>> +						   "pciclass0b03";
>>  
>>  				reg = <0x4800 0x0 0x0 0x0 0x0>;
>>  				#interrupt-cells = <1>;
>> @@ -163,10 +163,10 @@
>>  			};
>>  
>>  			pci_bridge@a,0 {
>> -				compatible = "pci0014,7a19.0",
>> -						   "pci0014,7a19",
>> -						   "pciclass060400",
>> -						   "pciclass0604";
>> +				compatible = "pci0014,7a09.0",
>> +						   "pci0014,7a09",
>> +						   "pciclass0b0300",
>> +						   "pciclass0b03";
>>  
>>  				reg = <0x5000 0x0 0x0 0x0 0x0>;
>>  				#interrupt-cells = <1>;
>> @@ -178,10 +178,10 @@
>>  			};
>>  
>>  			pci_bridge@b,0 {
>> -				compatible = "pci0014,7a19.0",
>> -						   "pci0014,7a19",
>> -						   "pciclass060400",
>> -						   "pciclass0604";
>> +				compatible = "pci0014,7a09.0",
>> +						   "pci0014,7a09",
>> +						   "pciclass0b0300",
>> +						   "pciclass0b03";
>>  
>>  				reg = <0x5800 0x0 0x0 0x0 0x0>;
>>  				#interrupt-cells = <1>;
>> @@ -193,10 +193,10 @@
>>  			};
>>  
>>  			pci_bridge@c,0 {
>> -				compatible = "pci0014,7a19.0",
>> -						   "pci0014,7a19",
>> -						   "pciclass060400",
>> -						   "pciclass0604";
>> +				compatible = "pci0014,7a09.0",
>> +						   "pci0014,7a09",
>> +						   "pciclass0b0300",
>> +						   "pciclass0b03";
>>  
>>  				reg = <0x6000 0x0 0x0 0x0 0x0>;
>>  				#interrupt-cells = <1>;
>> @@ -210,8 +210,8 @@
>>  			pci_bridge@d,0 {
>>  				compatible = "pci0014,7a19.0",
>>  						   "pci0014,7a19",
>> -						   "pciclass060400",
>> -						   "pciclass0604";
>> +						   "pciclass0b0300",
>> +						   "pciclass0b03";
>>  
>>  				reg = <0x6800 0x0 0x0 0x0 0x0>;
>>  				#interrupt-cells = <1>;
>> @@ -223,10 +223,10 @@
>>  			};
>>  
>>  			pci_bridge@e,0 {
>> -				compatible = "pci0014,7a19.0",
>> -						   "pci0014,7a19",
>> -						   "pciclass060400",
>> -						   "pciclass0604";
>> +				compatible = "pci0014,7a09.0",
>> +						   "pci0014,7a09",
>> +						   "pciclass0b0300",
>> +						   "pciclass0b03";
>>  
>>  				reg = <0x7000 0x0 0x0 0x0 0x0>;
>>  				#interrupt-cells = <1>;
>> -- 
>> 2.17.1
>>
>>
>
-- 
--xiaochuan