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[23.128.96.18]) by mx.google.com with ESMTP id f2si13784165plr.416.2021.04.25.05.37.53; Sun, 25 Apr 2021 05:38:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=vcPKbD3u; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230195AbhDYMg6 (ORCPT + 99 others); Sun, 25 Apr 2021 08:36:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230170AbhDYMg6 (ORCPT ); Sun, 25 Apr 2021 08:36:58 -0400 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD183C061574; Sun, 25 Apr 2021 05:36:18 -0700 (PDT) Received: by mail-pl1-x630.google.com with SMTP id n10so16343350plc.0; Sun, 25 Apr 2021 05:36:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pL2wYs0FKur1p37EfD6cIh4PXL/x/Qnvjj6a9pn8Rhw=; b=vcPKbD3uYSyFmbEmeH3iuRLyx0UFO7iJ+ZFIQiRvKR5UoeJ0aIyKeUqfMyXkpe1eH9 rvkAHUcDUF4OOTMwOb8yZhOxJH/I1A3GIQeS8FU9164OWwQEsPEo9UaZuhGgyUSicj1H uaRFo7eFzPtbLWNF8KkQvHdtJJTxbrQx0rUb27VqnXQ/V2KAvGPwLY2T9XfgUOdihYx4 pc9yGXZGwN2Wbp1ZzvM7mvC4q8FWHaV59pE7K0zFlO9FtqW369p8AXE/1ueDiW6ZUIHQ N1b9ofXbqNa8Yhwqp5f/+dy3K82q90ukMPesLVcBSscWUTBoJpucGw5THyunYmcgGe2Z 0NLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pL2wYs0FKur1p37EfD6cIh4PXL/x/Qnvjj6a9pn8Rhw=; b=U8QPkB7UtPd1jsZf6haFKI8MRCyn1XwDk77tDYe8jpvqETgLI0PGxFitOgCMYBl2dy Q7vG6ONQ9qXaA91TNuB81mGBogJANOvM5xR9xtFjADkYl/qcimExDMBSnW6elTsEt5PM BPHfcr+fqsFmeWsJ24sNdJkvmzQy8MZOyysxa4K4FbSBaiUIdPykmBdVyr0+NV3bIy54 LywAiLLN6swC6SfplrN1wIHIENdw2JveUBJ78gaDZvJZyFkxzxfy41Nz/Wap2aFOWJaW TFcFSFIKAkXbJTIRmosKn0+AFrM3TDC3/w4lvvQcWxk2LC3eSPk/FBP4cSFzOwJLyFiq 3YMw== X-Gm-Message-State: AOAM531oABz9xdGK6YayWjA1c7AiGBZJJxWhyOu3cpcZSe1V4KK/vtNv rHsk1Wv8K+x2wWwQIXGn8sw= X-Received: by 2002:a17:90a:20b:: with SMTP id c11mr15368927pjc.183.1619354178453; Sun, 25 Apr 2021 05:36:18 -0700 (PDT) Received: from nj08008nbu.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id f135sm8767808pfa.102.2021.04.25.05.36.15 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Apr 2021 05:36:18 -0700 (PDT) From: Kevin Tang To: maarten.lankhorst@linux.intel.com, mripard@kernel.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, mark.rutland@arm.com, kevin3.tang@gmail.com Cc: orsonzhai@gmail.com, zhang.lyra@gmail.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v5 1/6] dt-bindings: display: add Unisoc's drm master bindings Date: Sun, 25 Apr 2021 20:36:02 +0800 Message-Id: <20210425123607.26537-2-kevin3.tang@gmail.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210425123607.26537-1-kevin3.tang@gmail.com> References: <20210425123607.26537-1-kevin3.tang@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kevin Tang The Unisoc DRM master device is a virtual device needed to list all DPU devices or other display interface nodes that comprise the graphics subsystem Unisoc's display pipeline have several components as below description, multi display controllers and corresponding physical interfaces. For different display scenarios, dpu0 and dpu1 maybe binding to different encoder. E.g: dpu0 and dpu1 both binding to DSI for dual mipi-dsi display; dpu0 binding to DSI for primary display, and dpu1 binding to DP for external display; Cc: Orson Zhai Cc: Chunyan Zhang Signed-off-by: Kevin Tang Reviewed-by: Rob Herring --- .../display/sprd/sprd,display-subsystem.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/sprd/sprd,display-subsystem.yaml diff --git a/Documentation/devicetree/bindings/display/sprd/sprd,display-subsystem.yaml b/Documentation/devicetree/bindings/display/sprd/sprd,display-subsystem.yaml new file mode 100644 index 000000000..3d107e943 --- /dev/null +++ b/Documentation/devicetree/bindings/display/sprd/sprd,display-subsystem.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/sprd/sprd,display-subsystem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Unisoc DRM master device + +maintainers: + - Kevin Tang + +description: | + The Unisoc DRM master device is a virtual device needed to list all + DPU devices or other display interface nodes that comprise the + graphics subsystem. + + Unisoc's display pipeline have several components as below description, + multi display controllers and corresponding physical interfaces. + For different display scenarios, dpu0 and dpu1 maybe binding to different + encoder. + + E.g: + dpu0 and dpu1 both binding to DSI for dual mipi-dsi display; + dpu0 binding to DSI for primary display, and dpu1 binding to DP for external display; + + +-----------------------------------------+ + | | + | +---------+ | + +----+ | +----+ +---------+ |DPHY/CPHY| | +------+ + | +----->+dpu0+--->+MIPI|DSI +--->+Combo +----->+Panel0| + |AXI | | +----+ +---------+ +---------+ | +------+ + | | | ^ | + | | | | | + | | | +-----------+ | + | | | | | + |APB | | +--+-+ +-----------+ +---+ | +------+ + | +----->+dpu1+--->+DisplayPort+--->+PHY+--------->+Panel1| + | | | +----+ +-----------+ +---+ | +------+ + +----+ | | + +-----------------------------------------+ + +properties: + compatible: + const: sprd,display-subsystem + + ports: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should contain a list of phandles pointing to display interface port + of DPU devices. + +required: + - compatible + - ports + +additionalProperties: false + +examples: + - | + display-subsystem { + compatible = "sprd,display-subsystem"; + ports = <&dpu_out>; + }; + -- 2.29.0