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Subject: Re: [PATCH v2 6/7] arm64: dts: rockchip: add core dtsi for RK3568 SoC
To:     Marc Zyngier <maz@kernel.org>
References: <20210425094216.25724-1-cl@rock-chips.com>
 <20210425094439.25895-1-cl@rock-chips.com> <87mttmslni.wl-maz@kernel.org>
From:   =?UTF-8?B?6ZmI5Lqu?= <cl@rock-chips.com>
Message-ID: <ee4172da-13a4-2a94-446f-cfdd937574c3@rock-chips.com>
Date:   Mon, 26 Apr 2021 17:21:33 +0800
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Hi Marc,

?? 2021/4/25 ????6:28, Marc Zyngier д??:
> As I reviewed a previous version of this series, please have the
> courtesy of cc'ing me on further revisions of this series.
I am really sorry, i will add you to the cc list on further revisions.
>
> On Sun, 25 Apr 2021 10:44:39 +0100,
> <cl@rock-chips.com> wrote:
>> From: Liang Chen <cl@rock-chips.com>
>>
>> RK3568 is a high-performance and low power quad-core application processor
>> designed for personal mobile internet device and AIoT equipments. This patch
>> add basic core dtsi file for it.
>>
>> We use scmi_clk for cortex-a55 instead of standard ARMCLK, so that
>> kernel/uboot/rtos can change cpu clk with the same code in ATF, and we will
>> enalbe a special high-performacne PLL when high frequency is required. The
>> smci_clk code is in ATF, and clkid for cpu is 0, as below:
>>
>>      cpu0: cpu@0 {
>>          device_type = "cpu";
>>          compatible = "arm,cortex-a55";
>>          reg = <0x0 0x0>;
>>          clocks = <&scmi_clk 0>;
>>      };
>>
>> Signed-off-by: Liang Chen <cl@rock-chips.com>
>> ---
>>   .../boot/dts/rockchip/rk3568-pinctrl.dtsi     | 3119 +++++++++++++++++
>>   arch/arm64/boot/dts/rockchip/rk3568.dtsi      |  812 +++++
>>   2 files changed, 3931 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
>>   create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi
> [...]
>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
>> new file mode 100644
>> index 000000000000..66cb50218ca1
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
>> @@ -0,0 +1,812 @@
> [...]
>
>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
>> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
>> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> +		arm,no-tick-in-suspend;
> My questions on this property still stand [1].

Yes, rk3568 will lose the system counter in suspend mode, we must 
retrieve system time from RTC.

rk3588 will fix this issue.

>
>> +	};
>> +
>> +	xin24m: xin24m {
>> +		compatible = "fixed-clock";
>> +		clock-frequency = <24000000>;
>> +		clock-output-names = "xin24m";
>> +		#clock-cells = <0>;
>> +	};
>> +
>> +	xin32k: xin32k {
>> +		compatible = "fixed-clock";
>> +		clock-frequency = <32768>;
>> +		clock-output-names = "xin32k";
>> +		pinctrl-0 = <&clk32k_out0>;
>> +		pinctrl-names = "default";
>> +		#clock-cells = <0>;
>> +	};
>> +
>> +	gic: interrupt-controller@fd400000 {
>> +		compatible = "arm,gic-v3";
>> +		reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
>> +		      <0x0 0xfd460000 0 0xc0000>; /* GICR */
>> +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +		interrupt-controller;
>> +		#interrupt-cells = <3>;
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
> My request for a full description of the GICA region still stands [1].
Thanks, i will test MSIs with "mbi-alias", then add relative property in 
the next version.
>
> Thanks,
>
> 	M.
>
> [1] https://lore.kernel.org/r/87o8e2sm1u.wl-maz@kernel.org
>