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[23.128.96.18]) by mx.google.com with ESMTP id gh13si14097209ejb.442.2021.04.26.09.27.26; Mon, 26 Apr 2021 09:27:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=PDFbP9lq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234264AbhDZQ1M (ORCPT + 99 others); Mon, 26 Apr 2021 12:27:12 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59408 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233736AbhDZQ1L (ORCPT ); Mon, 26 Apr 2021 12:27:11 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 13QGQEdK002086; Mon, 26 Apr 2021 11:26:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1619454374; bh=yFWHKiCHy3VbVuWb5lsVMmHTWel2ryI5DUDoaPR3OvY=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=PDFbP9lqQFkl9BM11wkfsju1ILtpJuKX9dliJLQsguAoO5TwoLo/njOTYYvmqZUEc wGiGUa00Lt1nrOzw7ZgaZ38oz0ZGzHHTB2qt2SC9dQqH4kTm5maitM2G9lc+mm4rk8 Wi7fGuaXxIfdmTIZWOJzPFO8WI6RyTJYZ21KGTNQ= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 13QGQEVE010146 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 26 Apr 2021 11:26:14 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Mon, 26 Apr 2021 11:26:14 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Mon, 26 Apr 2021 11:26:14 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 13QGQDGd067403; Mon, 26 Apr 2021 11:26:13 -0500 Date: Mon, 26 Apr 2021 21:56:12 +0530 From: Pratyush Yadav To: CC: Mark Brown , Miquel Raynal , Vignesh Raghavendra , Boris Brezillon , , Alexandre Torgue , , , , , Subject: Re: [PATCH 1/3] spi: spi-mem: add automatic poll status functions Message-ID: <20210426162610.erpt5ubeddx7paeq@ti.com> References: <20210426143934.25275-1-patrice.chotard@foss.st.com> <20210426143934.25275-2-patrice.chotard@foss.st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20210426143934.25275-2-patrice.chotard@foss.st.com> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 26/04/21 04:39PM, patrice.chotard@foss.st.com wrote: > From: Christophe Kerello > > With STM32 QSPI, it is possible to poll the status register of the device. > This could be done to offload the CPU during an operation (erase or > program a SPI NAND for example). > > spi_mem_poll_status API has been added to handle this feature. > > Signed-off-by: Christophe Kerello > Signed-off-by: Patrice Chotard > --- > drivers/spi/spi-mem.c | 34 ++++++++++++++++++++++++++++++++++ > include/linux/spi/spi-mem.h | 8 ++++++++ > 2 files changed, 42 insertions(+) > > diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c > index 1513553e4080..43dce4b0efa4 100644 > --- a/drivers/spi/spi-mem.c > +++ b/drivers/spi/spi-mem.c > @@ -743,6 +743,40 @@ static inline struct spi_mem_driver *to_spi_mem_drv(struct device_driver *drv) > return container_of(drv, struct spi_mem_driver, spidrv.driver); > } > > +/** > + * spi_mem_poll_status() - Poll memory device status > + * @mem: SPI memory device > + * @op: the memory operation to execute > + * @mask: status bitmask to ckeck > + * @match: status expected value Technically, (status & mask) expected value. Dunno if that is obvious enough to not spell out explicitly. > + * @timeout: timeout > + * > + * This function send a polling status request to the controller driver > + * > + * Return: 0 in case of success, -ETIMEDOUT in case of error, > + * -EOPNOTSUPP if not supported. > + */ > +int spi_mem_poll_status(struct spi_mem *mem, > + const struct spi_mem_op *op, > + u8 mask, u8 match, u16 timeout) > +{ > + struct spi_controller *ctlr = mem->spi->controller; > + int ret = -EOPNOTSUPP; > + > + if (ctlr->mem_ops && ctlr->mem_ops->poll_status) { You should call spi_mem_supports_op() before sending any ops to the controller. Invalid/unsupported ops can cause unexpected behavior. > + ret = spi_mem_access_start(mem); > + if (ret) > + return ret; > + > + ret = ctlr->mem_ops->poll_status(mem, op, mask, match, timeout); I wonder if it is better to let spi-mem core take care of the timeout part. On one hand it reduces code duplication on the driver side a little bit. Plus it makes sure drivers don't mess anything up with bad (or no) handling of the timeout. But on the other hand the interface becomes a bit awkward since you'd have to pass a struct completion around, and it isn't something particularly hard to get right either. What do you think? > + > + spi_mem_access_end(mem); > + } > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(spi_mem_poll_status); > + > static int spi_mem_probe(struct spi_device *spi) > { > struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver); > diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h > index 2b65c9edc34e..5f78917c0f68 100644 > --- a/include/linux/spi/spi-mem.h > +++ b/include/linux/spi/spi-mem.h > @@ -250,6 +250,7 @@ static inline void *spi_mem_get_drvdata(struct spi_mem *mem) > * the currently mapped area), and the caller of > * spi_mem_dirmap_write() is responsible for calling it again in > * this case. > + * @poll_status: poll memory device status > * > * This interface should be implemented by SPI controllers providing an > * high-level interface to execute SPI memory operation, which is usually the > @@ -274,6 +275,9 @@ struct spi_controller_mem_ops { > u64 offs, size_t len, void *buf); > ssize_t (*dirmap_write)(struct spi_mem_dirmap_desc *desc, > u64 offs, size_t len, const void *buf); > + int (*poll_status)(struct spi_mem *mem, > + const struct spi_mem_op *op, > + u8 mask, u8 match, u16 timeout); > }; > > /** > @@ -369,6 +373,10 @@ devm_spi_mem_dirmap_create(struct device *dev, struct spi_mem *mem, > void devm_spi_mem_dirmap_destroy(struct device *dev, > struct spi_mem_dirmap_desc *desc); > > +int spi_mem_poll_status(struct spi_mem *mem, > + const struct spi_mem_op *op, > + u8 mask, u8 match, u16 timeout); > + > int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv, > struct module *owner); -- Regards, Pratyush Yadav Texas Instruments Inc.