Received: by 2002:a05:6a10:a841:0:0:0:0 with SMTP id d1csp4276707pxy; Tue, 27 Apr 2021 00:41:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyqIZ+NIWhv8tjRR5wN7GIlY1X7fcmRLexTYHopF9dJS2gA7Y2rr52M9XEvpbbRFHgNES4o X-Received: by 2002:a17:906:7118:: with SMTP id x24mr21918268ejj.127.1619509295238; Tue, 27 Apr 2021 00:41:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619509295; cv=none; d=google.com; s=arc-20160816; b=RlSsUjMuGJJWGB1kK8J3UuluvcxW14EcQaBHvcESNJ/FRrdIP4NlI5tlZizfLP5MhF HFLguUnfJ3ZEbtXxYAYnBt7UIXUy3p4bvQf/B0Wy/rRi+4y4CDz+egiHKNesS8lmrOEN u5+wSfa8kgOjZjxR12RzKL821HXPkXFOM5uoegmF2gedjexNsFQGPN0rRBQPAw2JgNHb rxwUdbCKmk1Ib//+gFdsSUaOUBKP9Nvx+yi9fRiKYMt5VHmil1zNLQ8DWONz2PTkO4OR wdFH1gHSkg1t2pYwgplp8Kgp91qF2p6vR1gKS4PauHpdyBLjz6+LCmJoaa9a2ef89N1b v3Hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=LJ7pV2oczQ6PJcXoTYNW6Gyl+H5pd9L5AP2DwD7TssE=; b=fk8R9i0B9JRMGMST1Dt+nb2cRrKly0XiQ/G7ZR+pGHa+n61lYvkGP2ybdYvQE43dD+ wwnMjDCZ+BCgo64oC1Le9KhxTi/QRLj+KHTLJy3AFubYbFwQeXgBge2S+dIevWDcvgW0 uHF2QmpiTT/yMEiiFqAIpNqvJt3qFZmbGMSNTw84LsABybtr6At9DDrl4kUsCBQjxdN7 zGyc9Sc6xYxWkXGdtPsTk3Sx9qAwO7ivChf70HDa8nThljIimPPOElTQMh8RhSHwG0wj 21G+TZhSqX6rEtCc/BwlmD4NY0RswABKrKhEoShnPn7JUC4AhakWJfU0JNdCiW0mRy70 /5/Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id j16si2146783edj.357.2021.04.27.00.41.12; Tue, 27 Apr 2021 00:41:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234925AbhD0Hku (ORCPT + 99 others); Tue, 27 Apr 2021 03:40:50 -0400 Received: from lucky1.263xmail.com ([211.157.147.134]:34128 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236277AbhD0HjJ (ORCPT ); Tue, 27 Apr 2021 03:39:09 -0400 Received: from localhost (unknown [192.168.167.70]) by lucky1.263xmail.com (Postfix) with ESMTP id C60AAC81E1; Tue, 27 Apr 2021 15:38:23 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P26232T140422993086208S1619509101181570_; Tue, 27 Apr 2021 15:38:23 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <5a7cc61b9ed6016aa573b9a5f15c5883> X-RL-SENDER: jon.lin@rock-chips.com X-SENDER: jon.lin@rock-chips.com X-LOGIN-NAME: jon.lin@rock-chips.com X-FST-TO: broonie@kernel.org X-RCPT-COUNT: 8 X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-System-Flag: 0 From: Jon Lin To: broonie@kernel.org Cc: heiko@sntech.de, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@esmil.dk, Jon Lin Subject: [PATCH v2 8/8] spi: rockchip: Support SPI_CS_HIGH Date: Tue, 27 Apr 2021 15:38:20 +0800 Message-Id: <20210427073820.31797-3-jon.lin@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210427073820.31797-1-jon.lin@rock-chips.com> References: <20210427073733.31419-1-jon.lin@rock-chips.com> <20210427073820.31797-1-jon.lin@rock-chips.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 1.Add standard spi-cs-high support 2.Refer to spi-controller.yaml for details Signed-off-by: Jon Lin --- drivers/spi/spi-rockchip.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 2b68691157d0..9d60c1b275e8 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -108,6 +108,8 @@ #define CR0_OPM_MASTER 0x0 #define CR0_OPM_SLAVE 0x1 +#define CR0_SOI_OFFSET 23 + #define CR0_MTM_OFFSET 0x21 /* Bit fields in SER, 2bit */ @@ -238,7 +240,7 @@ static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) { struct spi_controller *ctlr = spi->controller; struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); - bool cs_asserted = !enable; + bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable; /* Return immediately for no-op */ if (cs_asserted == rs->cs_asserted[spi->chip_select]) @@ -509,6 +511,8 @@ static int rockchip_spi_config(struct rockchip_spi *rs, cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET; if (spi->mode & SPI_LSB_FIRST) cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET; + if (spi->mode & SPI_CS_HIGH) + cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET; if (xfer->rx_buf && xfer->tx_buf) cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET; @@ -787,7 +791,7 @@ static int rockchip_spi_probe(struct platform_device *pdev) ctlr->auto_runtime_pm = true; ctlr->bus_num = pdev->id; - ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST; + ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST | SPI_CS_HIGH; if (slave_mode) { ctlr->mode_bits |= SPI_NO_CS; ctlr->slave_abort = rockchip_spi_slave_abort; -- 2.17.1