Date: Thu, 19 Oct 2006 15:59:39 -0700 (PDT)
Message-Id: <20061019.155939.48528489.davem@davemloft.net>
To: ralf@linux-mips.org
Cc: nickpiggin@yahoo.com.au, torvalds@osdl.org, akpm@osdl.org,
       linux-kernel@vger.kernel.org, anemo@mba.ocn.ne.jp
Subject: Re: [PATCH 1/3] Fix COW D-cache aliasing on fork
From: David Miller <davem@davemloft.net>
In-Reply-To: <20061019181346.GA5421@linux-mips.org>
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	<4537B9FB.7050303@yahoo.com.au>
	<20061019181346.GA5421@linux-mips.org>
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From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 19 Oct 2006 19:13:46 +0100

> That would require changing the order of cache flush and tlb flush.
> To keep certain architectures that require a valid translation in
> the TLB the cacheflush has to be done first.  Not sure if those
> architectures need a writeable mapping for dirty cachelines - I
> think hypersparc was one of them.

There just has to be "a mapping" in the TLB so that the L2 cache can
translate the virtual address to a physical one for the writeback to
main memory.
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