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Date:   Thu, 29 Apr 2021 08:40:43 +0100
Message-ID: <87eeeto7wk.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
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Subject: Re: [PATCH v3 09/10] arm64: dts: rockchip: add core dtsi for RK3568 SoC
In-Reply-To: <3401442c-24a1-e8f8-fc4a-fa44d94b903b@rock-chips.com>
References: <20210428134759.22076-1-cl@rock-chips.com>
        <20210428135002.22528-1-cl@rock-chips.com>
        <87h7jqo3d2.wl-maz@kernel.org>
        <3401442c-24a1-e8f8-fc4a-fa44d94b903b@rock-chips.com>
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On Thu, 29 Apr 2021 02:13:35 +0100,
陈亮 <cl@rock-chips.com> wrote:
> 
> Hi Marc,
> 
> 在 2021/4/28 下午11:06, Marc Zyngier 写道:
> > On Wed, 28 Apr 2021 14:50:02 +0100,
> > <cl@rock-chips.com> wrote:
> >> From: Liang Chen <cl@rock-chips.com>
> >> 
> >> RK3568 is a high-performance and low power quad-core application processor
> >> designed for personal mobile internet device and AIoT equipment. This patch
> >> add basic core dtsi file for it.
> >> 
> >> We use scmi_clk for cortex-a55 instead of standard ARMCLK, so that
> >> kernel/uboot/rtos can change cpu clk with the same code in ATF, and we will
> >> enalbe a special high-performance PLL when high frequency is required. The
> >> smci_clk code is in ATF, and clkid for cpu is 0, as below:
> >> 
> >>      cpu0: cpu@0 {
> >>          device_type = "cpu";
> >>          compatible = "arm,cortex-a55";
> >>          reg = <0x0 0x0>;
> >>          clocks = <&scmi_clk 0>;
> >>      };
> >> 
> >> Signed-off-by: Liang Chen <cl@rock-chips.com>
> >> ---
> >>   .../boot/dts/rockchip/rk3568-pinctrl.dtsi     | 3111 +++++++++++++++++
> >>   arch/arm64/boot/dts/rockchip/rk3568.dtsi      |  779 +++++
> >>   2 files changed, 3890 insertions(+)
> >>   create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> >>   create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi
> > [...]
> > 
> >> +	gic: interrupt-controller@fd400000 {
> >> +		compatible = "arm,gic-v3";
> >> +		reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
> >> +		      <0x0 0xfd460000 0 0xc0000>; /* GICR */
> > If this SoC has 4 CPUs, that's 4 redistributors. Given that GIC600
> > doesn't implement VLPIs, that's 128kB per redistributors. Why is GICR
> > large enough for 6 CPUs here? Is that copy-pasted from another SoC?
> Copy from rk3399, sorry.
> >> +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> >> +		interrupt-controller;
> >> +		#interrupt-cells = <3>;
> >> +		mbi-alias = <0x0 0xfd400000>;
> >> +		mbi-ranges = <296 24>;
> >> +		msi-controller;
> >> +	};
> > Glad to see that you found some spare SPIs to get MSIs going
> > 
> > However, the whole point of mbi-alias (aka GICA in GIC600) is to be
> > different from GICD and provide some isolation via an IOMMU.  If I
> > trust the TRM, if should be at 0xfd10000 in your implementation.
> 
> But in the ./devicetree/bindings/interrupt-controller/arm,gic-v3.yaml, say:
> 
>   mbi-alias:
>     description:
>       Address property. Base address of an alias of the *GICD* region
> containing
>       only the {SET,CLR}SPI registers to be used if isolation is required,
>       and if supported by the HW.


[recurring theme: I happen to know about this section of the binding,
having written the original myself]

How does that contradict my comment? GIC600's GICA page only contains
the four {SET,CLR}_SPI registers, as expected (see section 4.3 in the
TRM[1]), and the address is computed using table 4-1 "Register map
pages" of the same document.

Please either fix the DT or explain why the GICA distributor alias
isn't usable.

	M.

[1] https://documentation-service.arm.com/static/5e7ddddacbfe76649ba53034

-- 
Without deviation from the norm, progress is not possible.