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Date:   Fri, 30 Apr 2021 14:44:37 -0500
From:   Rob Herring <robh@kernel.org>
To:     Samuel Holland <samuel@sholland.org>
Cc:     Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
        Jernej Skrabec <jernej.skrabec@siol.net>,
        Felipe Balbi <balbi@kernel.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-sunxi@lists.linux.dev, linux-usb@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] dt-bindings: usb: Document the Allwinner H6 DWC3
 glue
Message-ID: <20210430194437.GA3755541@robh.at.kernel.org>
References: <20210430031912.42252-1-samuel@sholland.org>
 <20210430031912.42252-2-samuel@sholland.org>
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On Thu, Apr 29, 2021 at 10:19:11PM -0500, Samuel Holland wrote:
> The RST_BUS_XHCI reset line in the H6 affects both the DWC3 core and the
> USB3 PHY. This suggests the reset line controls the USB3 IP as a whole.
> Represent this by attaching the reset line to a glue layer device.

Does that really mean anything more than a shared reset? Doesn't the 
reset code support shared resets?

> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
>  .../usb/allwinner,sun50i-h6-dwc3.yaml         | 75 +++++++++++++++++++
>  1 file changed, 75 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/allwinner,sun50i-h6-dwc3.yaml
> 
> diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun50i-h6-dwc3.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun50i-h6-dwc3.yaml
> new file mode 100644
> index 000000000000..936b5c74043f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/allwinner,sun50i-h6-dwc3.yaml
> @@ -0,0 +1,75 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/allwinner,sun50i-h6-dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Allwinner H6 DWC3 USB controller
> +
> +maintainers:
> +  - Chen-Yu Tsai <wens@csie.org>
> +  - Maxime Ripard <mripard@kernel.org>
> +
> +properties:
> +  compatible:
> +    const: allwinner,sun50i-h6-dwc3
> +
> +  "#address-cells": true
> +
> +  "#size-cells": true
> +
> +  ranges: true
> +
> +  resets:
> +    maxItems: 1
> +
> +# Required child node:
> +
> +patternProperties:
> +  "^phy@[0-9a-f]+$":
> +    $ref: ../phy/allwinner,sun50i-h6-usb3-phy.yaml#
> +
> +  "^usb@[0-9a-f]+$":
> +    $ref: snps,dwc3.yaml#
> +
> +required:
> +  - compatible
> +  - ranges
> +  - resets
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/sun50i-h6-ccu.h>
> +    #include <dt-bindings/reset/sun50i-h6-ccu.h>
> +
> +    usb3: usb@5200000 {
> +        compatible = "allwinner,sun50i-h6-dwc3";
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        ranges;
> +        resets = <&ccu RST_BUS_XHCI>;
> +
> +        dwc3: usb@5200000 {
> +            compatible = "snps,dwc3";
> +            reg = <0x05200000 0x10000>;
> +            interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> +            clocks = <&ccu CLK_BUS_XHCI>,
> +                     <&ccu CLK_BUS_XHCI>,
> +                     <&rtc 0>;
> +            clock-names = "ref", "bus_early", "suspend";
> +            dr_mode = "host";
> +            phys = <&usb3phy>;
> +            phy-names = "usb3-phy";
> +        };
> +
> +        usb3phy: phy@5210000 {
> +            compatible = "allwinner,sun50i-h6-usb3-phy";
> +            reg = <0x5210000 0x10000>;
> +            clocks = <&ccu CLK_USB_PHY1>;
> +            resets = <&ccu RST_USB_PHY1>;
> +            #phy-cells = <0>;
> +        };
> +    };
> -- 
> 2.26.3
>