Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates
 216.228.112.34 as permitted sender) receiver=protection.outlook.com;
 client-ip=216.228.112.34; helo=mail.nvidia.com;
Subject: Re: [PATCH 02/16] PCI/P2PDMA: Avoid pci_get_slot() which sleeps
To:     Logan Gunthorpe <logang@deltatee.com>,
        <linux-kernel@vger.kernel.org>, <linux-nvme@lists.infradead.org>,
        <linux-block@vger.kernel.org>, <linux-pci@vger.kernel.org>,
        <linux-mm@kvack.org>, <iommu@lists.linux-foundation.org>
CC:     Stephen Bates <sbates@raithlin.com>,
        Christoph Hellwig <hch@lst.de>,
        Dan Williams <dan.j.williams@intel.com>,
        Jason Gunthorpe <jgg@ziepe.ca>,
        =?UTF-8?Q?Christian_K=c3=b6nig?= <christian.koenig@amd.com>,
        Don Dutile <ddutile@redhat.com>,
        Matthew Wilcox <willy@infradead.org>,
        Daniel Vetter <daniel.vetter@ffwll.ch>,
        Jakowski Andrzej <andrzej.jakowski@intel.com>,
        Minturn Dave B <dave.b.minturn@intel.com>,
        Jason Ekstrand <jason@jlekstrand.net>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Xiong Jianxin <jianxin.xiong@intel.com>,
        Bjorn Helgaas <helgaas@kernel.org>,
        Ira Weiny <ira.weiny@intel.com>,
        Robin Murphy <robin.murphy@arm.com>
References: <20210408170123.8788-1-logang@deltatee.com>
 <20210408170123.8788-3-logang@deltatee.com>
 <d6220bff-83fc-6c03-76f7-32e9e00e40fd@nvidia.com>
 <d4091d87-7d9e-8cde-4e1c-01b877b6785f@deltatee.com>
From:   John Hubbard <jhubbard@nvidia.com>
Message-ID: <b40529f9-03d8-ab61-4f4d-8f5bd8f860c9@nvidia.com>
Date:   Mon, 3 May 2021 11:20:30 -0700
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101
 Thunderbird/78.10.0
MIME-Version: 1.0
In-Reply-To: <d4091d87-7d9e-8cde-4e1c-01b877b6785f@deltatee.com>
Content-Type: text/plain; charset="utf-8"; format=flowed
Content-Language: en-US
Content-Transfer-Encoding: 7bit
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2021 18:20:31.4299
 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: 79acc9a7-e96c-4828-413d-08d90e6022ed
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com]
X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT044.eop-nam11.prod.protection.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Anonymous
X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem
X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3589
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On 5/3/21 9:08 AM, Logan Gunthorpe wrote:
...
>> By the way, pre-existing code comment: pci_p2pdma_whitelist[] seems
>> really short. From a naive point of view, I'd expect that there must be
>> a lot more CPUs/chipsets that can do pci p2p, what do you think? I
>> wonder if we have to be so super strict, anyway. It just seems extremely
>> limited, and I suspect there will be some additions to the list as soon
>> as we start to use this.
> 
> Yes, well unfortunately we have no other way to determine what host
> bridges can communicate with P2P. We settled on a whitelist when the
> series was first patch. Nobody likes that situation, but nobody has
> found anything better. We've been hoping standards bodies would give us
> a flag but I haven't heard anything about that. At least AMD has been
> able to guarantee us that all CPUs newer than Zen will support so that
> covers a large swath. It would be nice if we could say something similar
> for Intel.

Thanks for explaining the situation!

> 
>> OK, yes this avoids taking the pci_bus_sem, but it's kind of cheating.
>> Why is it OK to avoid taking any locks in order to retrieve the
>> first entry from the list, but in order to retrieve any other entry, you
>> have to aquire the pci_bus_sem, and get a reference as well? Something
>> is inconsistent there.
>>
>> The new version here also no longer takes a reference on the device,
>> which is also cheating. But I'm guessing that the unstated assumption
>> here is that there is always at least one entry in the list. But if
>> that's true, then it's better to show clearly that assumption, instead
>> of hiding it in an implicit call that skips both locking and reference
>> counting.
> 
> Because we hold a reference to a child device of the bus. So the host
> bus device can't go away until the child device has been released. An
> earlier version of the P2PDMA patchset had a lot more extraneous get
> device calls until someone else pointed this out.
> 
>> You could add a new function, which is a cut-down version of pci_get_slot(),
>> like this, and call this from __host_bridge_whitelist():
>>
>> /*
>>    * A special purpose variant of pci_get_slot() that doesn't take the pci_bus_sem
>>    * lock, and only looks for the 00.0 bus-device-function. Once the PCI bus is
>>    * up, it is safe to call this, because there will always be a top-level PCI
>>    * root device.
>>    *
>>    * Other assumptions: the root device is the first device in the list, and the
>>    * root device is numbered 00.0.
>>    */
>> struct pci_dev *pci_get_root_slot(struct pci_bus *bus)
>> {
>> 	struct pci_dev *root;
>> 	unsigned devfn = PCI_DEVFN(0, 0);
>>
>> 	root = list_first_entry_or_null(&bus->devices, struct pci_dev,
>> 					bus_list);
>> 	if (root->devfn == devfn)
>> 		goto out;
>>
>> 	root = NULL;
>>    out:
>> 	pci_dev_get(root);
>> 	return root;
>> }
>> EXPORT_SYMBOL(pci_get_root_slot);
>>
>> ...I think that's a lot clearer to the reader, about what's going on here.
> 
> Per above, I think the reference count is unnecessary. But I could wrap
> it in a static function for clarity. (There's no reason to export this
> function).
> 

Yes, please.


thanks,
-- 
John Hubbard
NVIDIA