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Tue, 4 May 2021 16:31:47 +0000 Received: from BY5PR12MB3827.namprd12.prod.outlook.com ([fe80::81ef:d824:43ae:aef5]) by BY5PR12MB3827.namprd12.prod.outlook.com ([fe80::81ef:d824:43ae:aef5%4]) with mapi id 15.20.4087.044; Tue, 4 May 2021 16:31:47 +0000 Date: Tue, 4 May 2021 13:31:45 -0300 From: Jason Gunthorpe To: Jacob Pan Cc: "Tian, Kevin" , Alex Williamson , "Liu, Yi L" , Auger Eric , Jean-Philippe Brucker , LKML , Joerg Roedel , Lu Baolu , David Woodhouse , "iommu@lists.linux-foundation.org" , "cgroups@vger.kernel.org" , Tejun Heo , Li Zefan , Johannes Weiner , Jean-Philippe Brucker , Jonathan Corbet , "Raj, Ashok" , "Wu, Hao" , "Jiang, Dave" Subject: Re: [PATCH V4 05/18] iommu/ioasid: Redefine IOASID set and allocation APIs Message-ID: <20210504163145.GU1370958@nvidia.com> References: <20210421230301.GP1370958@nvidia.com> <20210422121020.GT1370958@nvidia.com> <20210423114944.GF1370958@nvidia.com> <20210426123817.GQ1370958@nvidia.com> <20210428204606.GX1370958@nvidia.com> <20210504092255.76c387f8@jacob-builder> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?mydIjh5YQxEaSIEivDI+tYfJOdWSzL3ZMmQ7UxOd7KRuzIiuNTVkVu5cEC5M?= =?us-ascii?Q?SJeh8o/Y58ZDvQtDyAZwVEEn+/X737qwRZjOrzgtVRrSHbJJbFS6WBGpo3dF?= =?us-ascii?Q?nvcbHa8aQv9pAfnkvw4SLD304VZMrRfN5u0KCQ97QGzrYlv/pUWnJVxIlT1O?= =?us-ascii?Q?nF9AtK6BDrsaqRumll8SSXT5tu4Qim93FkAmtZPoRDjbXaJQ7O8Geqyi/9tp?= =?us-ascii?Q?XukfiXIYEzzKWGHHl0IIKIQw8+hd45Yru0x0uRTTlduy/NeVp/1VFL7A9eZu?= =?us-ascii?Q?N9Y9UP2oKAxCCktcs6L549/QpRF9jg6MbmyYcNFUQQZOOr0OweyTYMBkZkDu?= =?us-ascii?Q?NO3lqntCiRbE1tBW4AQwUlWlVbxT4aI+Af4OohlzVtE/qUDmWRJtZdRu9vpC?= =?us-ascii?Q?133k4C6hNpKrEoI08M1BO5Eov5vNg/jpb+//Da3T0eS+CTbeQD008x4c/igt?= =?us-ascii?Q?DPTyn2N6esYjNx+Uc8dbX9TCbGtJlVZtJq2RBEgSTJ8uzimCZ8ygBwzr6Ywr?= =?us-ascii?Q?dyj2k9fy+qgJ0Z5ppOgs7mv87/lU1JLIgGqZsFOKdE066NUNPBJU70BBiA+1?= =?us-ascii?Q?tamb34TTMlPdzPZ4oN35TWoQ6Ba0Ny1oBii9JU0un8B6VEUjateh1fg4jIWy?= =?us-ascii?Q?1xra/9zctPAWIXibydbw4rWIZKSUNOeungu2uPdloIUqI9tIiFVF++l8+tl6?= =?us-ascii?Q?4Onxqt6OBw9o9L/RhIYTdtsKsf0nuvNEu/1xSM9GI0r0u10z+QCVCaZoGC1p?= =?us-ascii?Q?faVgJv//PVAvlienNVqW0s0VtastyMG0uUcx9Ut8MXTEkeovVhp8F682zzEF?= =?us-ascii?Q?EU7FXSZMtyM6Xuq3ihZc9I3yn9leRHdjNwE/VQBUH93be48/XWBRcDY37Oel?= =?us-ascii?Q?0EItLNlf+vyMiVRz8ak30qLT1B0x/IzufMzGOSrBd8TUDRwscM/ZSe9scWuR?= =?us-ascii?Q?JlWJyraSS5SBjOUGA6g6H9E1O4R0cBNqdMq911RMHcSgwhqZAuzLINWumh2Y?= =?us-ascii?Q?Nuzwb8L6j/pvUgNvvor/ye81COUwPnSbM87xWqGi2+7/t7chkuz3KBhPJlq/?= =?us-ascii?Q?cPMbC82g3ouJMzzfuBu5uzgnQhOfC/kQVi1TmI/6pFp6UNucPENW6mLvtCx+?= =?us-ascii?Q?cvbicEZ+F8Asb6RNMfSoFrVdDq2QwdE2Z7Lot2hPvSR78Lgp3cUruXK06Led?= =?us-ascii?Q?vRB4X3tJ8SSH3vIBldhuR3kq0RUSiS0C1srlKxR3SNzaTtIu1NTUPrETwJam?= =?us-ascii?Q?eUo54TLQ74kbgIeTldGvxfh3pExTm0AMX4Ozlc6Z/ewhxG46qdHRQWOxJqAl?= =?us-ascii?Q?a9A7FbfRQtOT0Bk+NcN1VlRw?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: a1aae10c-c672-4dde-f67d-08d90f1a1c9a X-MS-Exchange-CrossTenant-AuthSource: BY5PR12MB3827.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2021 16:31:47.5778 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +ZTbqUqBPVaOm0gcTie4BYe2Ke+K6ZNz288TCg+a1N4Cgg2PXJL0j2W18oVBIfNB X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4241 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 04, 2021 at 09:22:55AM -0700, Jacob Pan wrote: > Hi Jason, > > On Wed, 28 Apr 2021 17:46:06 -0300, Jason Gunthorpe wrote: > > > > > I think the name IOASID is fine for the uAPI, the kernel version can > > > > be called ioasid_id or something. > > > > > > ioasid is already an id and then ioasid_id just adds confusion. Another > > > point is that ioasid is currently used to represent both PCI PASID and > > > ARM substream ID in the kernel. It implies that if we want to separate > > > ioasid and pasid in the uAPI the 'pasid' also needs to be replaced with > > > another general term usable for substream ID. Are we making the > > > terms too confusing here? > > > > This is why I also am not so sure about exposing the PASID in the API > > because it is ultimately a HW specific item. > > > > As I said to David, one avenue is to have some generic uAPI that is > > very general and keep all this deeply detailed stuff, that really only > > matters for qemu, as part of a more HW specific vIOMMU driver > > interface. > I think it is not just for QEMU. I am assuming you meant PASID is > needed for guest driver to program assigned but not mediated devices. Anything that directly operates the device and tries to instantiate PASIDs for vfio-pci devices will need to understand the PASID. > User space drivers may also need to get the real HW PASID to program it on > to the HW. So this uAPI need to provide some lookup functionality. Perhaps > the kernel generic version can be called ioasid_hw_id? > > So we have the following per my understanding: > - IOASID: a userspace logical number which identifies a page table, this can > be a first level (GVA-GPA), or a second level (GPA->HPA) page table. > - PASID: strictly defined in PCIe term > - Substream ID: strictly defined in ARM SMMUv3 spec. > - IOASID_HW_ID: a generic ID backed by PASID, Substream ID, or any other > HW IDs used to tag DMA > > Is that right? It is reasonable. If a IOASID_HW_ID IOCTL can back with a enum that qualified its exact nature it might be perfectly fine. Jason