Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: quoted-printable
From:   Andy Lutomirski <luto@amacapital.net>
Mime-Version: 1.0 (1.0)
Subject: Re: [PATCH] KVM/VMX: Invoke NMI non-IST entry instead of IST entry
Date:   Tue, 4 May 2021 18:11:33 -0700
Message-Id: <2FB0C052-A998-4510-8BBA-6B48AC86E4C8@amacapital.net>
References: <CAJhGHyDsTVyDX9fkYAyVkVQFWqkyTAVCY4enJqdG4bzOuOSn+w@mail.gmail.com>
Cc:     Sean Christopherson <seanjc@google.com>,
        Paolo Bonzini <pbonzini@redhat.com>,
        Maxim Levitsky <mlevitsk@redhat.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        LKML <linux-kernel@vger.kernel.org>,
        Lai Jiangshan <laijs@linux.alibaba.com>,
        Steven Rostedt <rostedt@goodmis.org>,
        Andi Kleen <ak@linux.intel.com>,
        Andy Lutomirski <luto@kernel.org>,
        Vitaly Kuznetsov <vkuznets@redhat.com>,
        Wanpeng Li <wanpengli@tencent.com>,
        Jim Mattson <jmattson@google.com>,
        Joerg Roedel <joro@8bytes.org>,
        Josh Poimboeuf <jpoimboe@redhat.com>,
        Uros Bizjak <ubizjak@gmail.com>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        X86 ML <x86@kernel.org>, "H. Peter Anvin" <hpa@zytor.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Alexandre Chartre <alexandre.chartre@oracle.com>,
        Juergen Gross <JGross@suse.com>,
        Joerg Roedel <jroedel@suse.de>, Jian Cai <caij2003@gmail.com>
In-Reply-To: <CAJhGHyDsTVyDX9fkYAyVkVQFWqkyTAVCY4enJqdG4bzOuOSn+w@mail.gmail.com>
To:     Lai Jiangshan <jiangshanlai@gmail.com>
Precedence: bulk


> On May 4, 2021, at 6:08 PM, Lai Jiangshan <jiangshanlai@gmail.com> wrote:
>=20
> =EF=BB=BFOn Wed, May 5, 2021 at 5:23 AM Andy Lutomirski <luto@amacapital.n=
et> wrote:
>>=20
>>=20
>>>> On May 4, 2021, at 2:21 PM, Sean Christopherson <seanjc@google.com> wro=
te:
>>>=20
>>> =EF=BB=BFOn Tue, May 04, 2021, Paolo Bonzini wrote:
>>>>> On 04/05/21 23:05, Maxim Levitsky wrote:
>>>>> Does this mean that we still rely on hardware NMI masking to be activa=
ted?
>>>>=20
>>>> No, the NMI code already handles reentrancy at both the assembly and C
>>>> levels.
>>>>=20
>>>>> Or in other words, that is we still can't have an IRET between VM exit=
 and
>>>>> the entry to the NMI handler?
>>>>=20
>>>> No, because NMIs are not masked on VM exit.  This in fact makes things
>>>> potentially messy; unlike with AMD's CLGI/STGI, only MSRs and other thi=
ngs
>>>> that Intel thought can be restored atomically with the VM exit.
>>>=20
>>> FWIW, NMIs are masked if the VM-Exit was due to an NMI.
>>=20
>> Then this whole change is busted, since nothing will unmask NMIs. Revert i=
t?
>=20
> There is some instructable code between VMEXIT and
> handle_exception_nmi_irqoff().
>=20
> The possible #DB #BP can happen in this gap and the IRET
> of the handler of #DB #BP will unmask NMI.
>=20
> Another way to fix is to change the VMX code to call the NMI handler
> immediately after VMEXIT before leaving "nostr" section.
>=20
> Reverting it can't fix the problem.

I was indeed wrong, and the helper properly unmasks NMIs. So all should be w=
ell.

I will contemplate how this all interacts with FRED.=