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Subject: Re: [PATCH v4 1/1] x86/cpufeatures: Implement Predictive Store
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To:     Pawan Gupta <writetopawan@gmail.com>
Cc:     linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de,
        mingo@redhat.com, bp@alien8.de, hpa@zytor.com,
        Jonathan Corbet <corbet@lwn.net>, bsd@redhat.com
References: <20210430131733.192414-1-rsaripal@amd.com>
 <20210430131733.192414-2-rsaripal@amd.com>
 <20210505001154.rmibherzitm2yaga@devbox.home>
From:   "Saripalli, RK" <rsaripal@amd.com>
Message-ID: <03c5cd2b-ae83-1d7e-0761-81055d281b78@amd.com>
Date:   Tue, 4 May 2021 20:11:06 -0500
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On 5/4/2021 7:11 PM, Pawan Gupta wrote:
> On 30.04.2021 08:17, Ramakrishna Saripalli wrote:
>> --- a/arch/x86/kernel/cpu/amd.c
>> +++ b/arch/x86/kernel/cpu/amd.c
>> @@ -1170,3 +1170,26 @@ void set_dr_addr_mask(unsigned long mask, int dr)
>>         break;
>>     }
>> }
>> +
>> +static int __init psf_cmdline(char *str)
>> +{
>> +    u64 tmp = 0;
>> +
>> +    if (!boot_cpu_has(X86_FEATURE_PSFD))
>> +        return 0;
>> +
>> +    if (!str)
>> +        return -EINVAL;
>> +
>> +    if (!strcmp(str, "off")) {
>> +        set_cpu_cap(&boot_cpu_data, X86_FEATURE_MSR_SPEC_CTRL);
>> +        rdmsrl(MSR_IA32_SPEC_CTRL, tmp);
>> +        tmp |= SPEC_CTRL_PSFD;
>> +        x86_spec_ctrl_base |= tmp;
> 
> I don't think there is a need to update x86_spec_ctrl_base here.
> check_bugs() already reads the MSR_IA32_SPEC_CTRL and updates
> x86_spec_ctrl_base.

Pawan, you are correct. I added the update to x86_spec_ctrl_base to ensure that the bits 
in x86_spec_ctrl_base are consistent with the actual bits in the MSR after this change

>> +        wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>> +early_param("predict_store_fwd", psf_cmdline);
>> diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
>> index d41b70fe4918..536136e0daa3 100644
>> --- a/arch/x86/kernel/cpu/bugs.c
>> +++ b/arch/x86/kernel/cpu/bugs.c
>> @@ -78,6 +78,8 @@ EXPORT_SYMBOL_GPL(mds_idle_clear);
>>
>> void __init check_bugs(void)
>> {
>> +    u64 tmp = 0;
>> +
>>     identify_boot_cpu();
>>
>>     /*
>> @@ -97,7 +99,9 @@ void __init check_bugs(void)
>>      * init code as it is not enumerated and depends on the family.
>>      */
>>     if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
>> -        rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
>> +        rdmsrl(MSR_IA32_SPEC_CTRL, tmp);
>> +
>> +    x86_spec_ctrl_base |= tmp;
> 
> This change also doesn't seem to be necessary, psf_cmdline() updates the
> MSR( i.e. sets PSFD).  Here read from the MSR will still update
> x86_spec_ctrl_base to the correct value. Am I missing something?

Yes you are correct because psf_cmdline executes before check_bugs() and does update
the MSR. 


> 
> Thanks,
> Pawan