Received: by 2002:a05:6a10:a852:0:0:0:0 with SMTP id d18csp385912pxy; Wed, 5 May 2021 04:48:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzuwP5Md5vFggDgQZ6D2NbvoTRSu267/AFvS79YbSV5lCJ4St5O/ysQaJs33vkifl0eiip9 X-Received: by 2002:a17:907:78c4:: with SMTP id kv4mr26683573ejc.445.1620215282462; Wed, 05 May 2021 04:48:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620215282; cv=none; d=google.com; s=arc-20160816; b=LlIlBInmnQkdsMstDDspZaLkg5+WKRmSJ5UMHmcDR23xsT3GlH97aaVvkRqz6OKiZu 4qSJnRDeu2sF7dOcmwiNCzakhLuGP9vWDAQH9kykDVsELaA5Ndf9nceAnDfq+yygnxi+ 5AFDZevmeQXJ+KtL+pWTd+VNmgw4lvBw7lgi2R38weNGXEcalbBnWJ2ZWxZGO/MDzzR3 tHAfc6x2tPE7rwEHsTyIs2oVj6bDuT3OvlpLqjKsZwK2SkSftBdIbZzSlp1DdPrtaqBw zvOiPEoGKsogwc7GSXsBLLIoZ0lrNLHmjEmIAdFCDqYmPyQwtutZT2xZQ29u9aM6//mZ hcmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:user-agent:in-reply-to:content-transfer-encoding :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=2f1f/vQ1ZrjZ6P1qyWf4iwFSzr1U8FwaN3przNQ8kgo=; b=VkQFd6LDBOOBsP/NMhSDTHz1TLMjwSKP8Kq6AGjK8jD6Hk0qq0pwVxrNZJ+gcsSPuZ OopfpuZOf04G/L3EARnPJxbi0DNTX0z/ZM35N5M3iY3w3Msh7YNZHsfJ7KatBc3QGO6q +xbXbWORRnlBH4MAVMyQ7+aZnFMaS38+rzK44gU4bx/DiRBMLL5FiMiTaXfD8+DRm/UZ Fzmfo18WL6zO3KV6WnPAy0OV/Kl1t3etvkogUo0dT7DPyCfWQ0zaJkETP1hJWjwiNyZz TWkZV+3xlx/HnHergxTNNO9l1M9dpqBG+2ESoDhccSGszRBxqz8ZTpOdPv15HK5HcuzW pwBg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w12si14563050edv.597.2021.05.05.04.47.35; Wed, 05 May 2021 04:48:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232987AbhEELpI (ORCPT + 99 others); Wed, 5 May 2021 07:45:08 -0400 Received: from foss.arm.com ([217.140.110.172]:43060 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232658AbhEELpH (ORCPT ); Wed, 5 May 2021 07:45:07 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 06D1F31B; Wed, 5 May 2021 04:44:11 -0700 (PDT) Received: from bogus (unknown [10.57.61.118]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1C77A3F70D; Wed, 5 May 2021 04:44:09 -0700 (PDT) Date: Wed, 5 May 2021 12:44:06 +0100 From: Sudeep Holla To: Viresh Kumar Cc: Sibi Sankar , bjorn.andersson@linaro.org, Sudeep Holla , swboyd@chromium.org, agross@kernel.org, robh+dt@kernel.org, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, mka@chromium.org Subject: Re: [PATCH 2/2] arm64: dts: qcom: sc7280: Add cpu OPP tables Message-ID: <20210505114406.dawq5xvhnc6ifetb@bogus> References: <1619792901-32701-1-git-send-email-sibis@codeaurora.org> <1619792901-32701-3-git-send-email-sibis@codeaurora.org> <20210504144215.svmrmmsy4jtoixzv@bogus> <1fc9fb8d9a94909ff9b7b76d598bd266@codeaurora.org> <20210505084908.3lynedmblmqagr72@bogus> <20210505113724.fpzcizgytf55msfa@vireshk-i7> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210505113724.fpzcizgytf55msfa@vireshk-i7> User-Agent: NeoMutt/20171215 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 05, 2021 at 05:07:24PM +0530, Viresh Kumar wrote: > On 05-05-21, 09:49, Sudeep Holla wrote: > > No my main concern is this platform uses "qcom-cpufreq-hw" driver and the > > fact that the OPPs are retrieved from the hardware lookup table invalidates > > whatever we have in DT. > > Not exactly. > > It disables them all, and then call dev_pm_opp_adjust_voltage() and > enable them again. This is how it started initially. Though the driver > also works if the DT doesn't have the table, in that case it calls > dev_pm_opp_add() for all the OPPs. > Ah OK, if it is handled in the driver, I will shut up then ????. I did a quick look at it but couldn't understand the connection, so I started and continued the discussion. Thanks for the confirmation. I am fine if it is handled. -- Regards, Sudeep