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From:   Adam Ford <aford173@gmail.com>
Date:   Wed, 5 May 2021 07:59:25 -0500
Message-ID: <CAHCN7xLSgkJKs-8baa9O303=x1jB=7khedyBMcoHP_33Obqdbg@mail.gmail.com>
Subject: Re: [PATCH] clk: vc5: fix output disabling when enabling a FOD
To:     Luca Ceresoli <luca@lucaceresoli.net>
Cc:     linux-clk <linux-clk@vger.kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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On Fri, Apr 9, 2021 at 7:57 AM Luca Ceresoli <luca@lucaceresoli.net> wrote:
>
> On 5P49V6965, when an output is enabled we enable the corresponding
> FOD. When this happens for the first time, and specifically when writing
> register VC5_OUT_DIV_CONTROL in vc5_clk_out_prepare(), all other outputs
> are stopped for a short time and then restarted.
>
> According to Renesas support this is intended: "The reason for that is VC=
6E
> has synced up all output function".
>
> This behaviour can be disabled at least on VersaClock 6E devices, of whic=
h
> only the 5P49V6965 is currently implemented by this driver. This requires
> writing bit 7 (bypass_sync{1..4}) in register 0x20..0x50.  Those register=
s
> are named "Unused Factory Reserved Register", and the bits are documented
> as "Skip VDDO<N> verification", which does not clearly explain the relati=
on
> to FOD sync. However according to Renesas support as well as my testing
> setting this bit does prevent disabling of all clock outputs when enablin=
g
> a FOD.
>
> See "VersaClock =C2=AE 6E Family Register Descriptions and Programming Gu=
ide"
> (August 30, 2018), Table 116 "Power Up VDD check", page 58:
> https://www.renesas.com/us/en/document/mau/versaclock-6e-family-register-=
descriptions-and-programming-guide
>
Reviewed-by: Adam Ford <aford173@gmail.com>

> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
> ---
>  drivers/clk/clk-versaclock5.c | 27 ++++++++++++++++++++++++---
>  1 file changed, 24 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.=
c
> index 344cd6c61188..3c737742c2a9 100644
> --- a/drivers/clk/clk-versaclock5.c
> +++ b/drivers/clk/clk-versaclock5.c
> @@ -69,7 +69,10 @@
>  #define VC5_FEEDBACK_FRAC_DIV(n)               (0x19 + (n))
>  #define VC5_RC_CONTROL0                                0x1e
>  #define VC5_RC_CONTROL1                                0x1f
> -/* Register 0x20 is factory reserved */
> +
> +/* These registers are named "Unused Factory Reserved Registers" */
> +#define VC5_RESERVED_X0(idx)           (0x20 + ((idx) * 0x10))
> +#define VC5_RESERVED_X0_BYPASS_SYNC    BIT(7) /* bypass_sync<idx> bit */
>
>  /* Output divider control for divider 1,2,3,4 */
>  #define VC5_OUT_DIV_CONTROL(idx)       (0x21 + ((idx) * 0x10))
> @@ -87,7 +90,6 @@
>  #define VC5_OUT_DIV_SKEW_INT(idx, n)   (0x2b + ((idx) * 0x10) + (n))
>  #define VC5_OUT_DIV_INT(idx, n)                (0x2d + ((idx) * 0x10) + =
(n))
>  #define VC5_OUT_DIV_SKEW_FRAC(idx)     (0x2f + ((idx) * 0x10))
> -/* Registers 0x30, 0x40, 0x50 are factory reserved */
>
>  /* Clock control register for clock 1,2 */
>  #define VC5_CLK_OUTPUT_CFG(idx, n)     (0x60 + ((idx) * 0x2) + (n))
> @@ -140,6 +142,8 @@
>  #define VC5_HAS_INTERNAL_XTAL  BIT(0)
>  /* chip has PFD requency doubler */
>  #define VC5_HAS_PFD_FREQ_DBL   BIT(1)
> +/* chip has bits to disable FOD sync */
> +#define VC5_HAS_BYPASS_SYNC_BIT        BIT(2)
>
>  /* Supported IDT VC5 models. */
>  enum vc5_model {
> @@ -581,6 +585,23 @@ static int vc5_clk_out_prepare(struct clk_hw *hw)
>         unsigned int src;
>         int ret;
>
> +       /*
> +        * When enabling a FOD, all currently enabled FODs are briefly
> +        * stopped in order to synchronize all of them. This causes a clo=
ck
> +        * disruption to any unrelated chips that might be already using
> +        * other clock outputs. Bypass the sync feature to avoid the issu=
e,
> +        * which is possible on the VersaClock 6E family via reserved
> +        * registers.
> +        */

Thanks for the comments here.  I with IDT/Renesas would better
document this. I might see if I can convince one of the hardware guys
at my office to test the impact of radiated emissions.

> +       if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) {
> +               ret =3D regmap_update_bits(vc5->regmap,
> +                                        VC5_RESERVED_X0(hwdata->num),
> +                                        VC5_RESERVED_X0_BYPASS_SYNC,
> +                                        VC5_RESERVED_X0_BYPASS_SYNC);
> +               if (ret)
> +                       return ret;
> +       }
> +
>         /*
>          * If the input mux is disabled, enable it first and
>          * select source from matching FOD.
> @@ -1166,7 +1187,7 @@ static const struct vc5_chip_info idt_5p49v6965_inf=
o =3D {
>         .model =3D IDT_VC6_5P49V6965,
>         .clk_fod_cnt =3D 4,
>         .clk_out_cnt =3D 5,
> -       .flags =3D 0,
> +       .flags =3D VC5_HAS_BYPASS_SYNC_BIT,
>  };
>
>  static const struct i2c_device_id vc5_id[] =3D {
> --
> 2.25.1
>