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From:   ira.weiny@intel.com
To:     Ben Widawsky <ben.widawsky@intel.com>,
        Dan Williams <dan.j.williams@intel.com>
Cc:     Ira Weiny <ira.weiny@intel.com>,
        Alison Schofield <alison.schofield@intel.com>,
        Vishal Verma <vishal.l.verma@intel.com>,
        Jonathan Cameron <Jonathan.Cameron@huawei.com>,
        linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 0/4] Map register blocks individually
Date:   Thu,  6 May 2021 15:36:50 -0700
Message-Id: <20210506223654.1310516-1-ira.weiny@intel.com>
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From: Ira Weiny <ira.weiny@intel.com>

User space will want to map some register blocks.  Currently BARs are mapped in
their entirety and pointers to the register blocks are created into those
mappings.  This will prevent mappings from user space.

This series has 3 clean up patches followed by a patch to mapping the register
blocks individually.

Unfortunately, the information for the register blocks is contained inside the
BARs themselves.  Which means the BAR must be mapped, probed, and unmapped
prior to the registers being mapped individually.

The probe stage creates list of register maps which is then iterated to map
the individual register blocks.

Ira Weiny (4):
  cxl/mem: Fully decode device capability header
  cxl/mem: Reserve all device regions at once
  cxl/mem: Introduce cxl_decode_register_block()
  cxl/mem: Map registers based on capabilities

 drivers/cxl/core.c |  84 ++++++++++++++++++++------
 drivers/cxl/cxl.h  |  34 +++++++++--
 drivers/cxl/pci.c  | 147 +++++++++++++++++++++++++++++++++++----------
 3 files changed, 211 insertions(+), 54 deletions(-)

-- 
2.28.0.rc0.12.gb6a658bd00c9