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[23.128.96.18]) by mx.google.com with ESMTP id 3si5157633pfh.72.2021.05.06.16.08.36; Thu, 06 May 2021 16:08:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=OxYRibS4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235925AbhEFPhB (ORCPT + 99 others); Thu, 6 May 2021 11:37:01 -0400 Received: from mail.kernel.org ([198.145.29.99]:45974 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235569AbhEFPdt (ORCPT ); Thu, 6 May 2021 11:33:49 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id E5B4C61492; Thu, 6 May 2021 15:32:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1620315171; bh=aFz0PFRzNP3wjEbTBW+rHPZjGLu0vSW7VtIiwAyNHNc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OxYRibS40Y+CZI4MoUELH9lWQ8j2mwyO/xAYa5r57x9HG7QjwBnWqqgF571Cj2Qh3 pO73bc6cDOzKIfndLOMgGZLgyXOHNDDGbsh6qod1XC1kgAouWp+b6kr4Qz52QMXO+o EOWfiBlZriNhtdAHZYOEMyCZdrP0nk0SHT3cCskKdv7xSeEUOy13iMNND+vJQN3P3X xrEzr93HeKB/krSkh3etvcp/xvgyhf8S+DmRHDhsenNWMsQ5pJoM4uYYMc4OEKE/No RcNqBH11zYEfdzz0dqTSatu4eBcLTS0RFw2Zdoc88+LulQSS0LFXEXY6GDY415sxei UAzv7yVZ9CfPA== Received: by pali.im (Postfix) id 9F939732; Thu, 6 May 2021 17:32:50 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Lorenzo Pieralisi , Thomas Petazzoni , Rob Herring , Bjorn Helgaas Cc: Russell King , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Remi Pommarel , Xogium , Tomasz Maciej Nowak , Marc Zyngier , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 22/42] PCI: aardvark: Enable MSI-X support Date: Thu, 6 May 2021 17:31:33 +0200 Message-Id: <20210506153153.30454-23-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210506153153.30454-1-pali@kernel.org> References: <20210506153153.30454-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org According to PCI 3.0 specification, sending both MSI and MSI-X interrupts is done by DWORD memory write operation to doorbell message address. The write operation for MSI has zero upper 16 bits and the MSI interrupt number in the lower 16 bits. The write operation for MSI-X contains a 32-bit value from MSI-X table. This means that when MSI-X uses only a 16-bit value, the MSI-X message can be captured by aardvark MSI doorbell address processing. Therefore aardvark HW should also support MSI-X interrupts, despite Armada 3700 Functional Specification not mentioning anything about how to configure PCIe for MSI-X interrupts. (Note that the specification says that MSI-X is supported, it just does not say explicitly how to enable it.) Since pci-aardvark.c driver now supports receiving MSI interrupt with any 16-bit number, enable also MSI-X support. Testing proved that kernel can correctly receive MSI-X interrupts from PCIe cards which supports both MSI and MSI-X interrupts. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 376f0666becc..8a5133226e41 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1082,7 +1082,7 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) msi_di = &pcie->msi_domain_info; msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_MULTI_PCI_MSI; + MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX; msi_di->chip = msi_ic; /* -- 2.20.1