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Date:   Fri, 7 May 2021 16:31:32 +0100
From:   Mark Brown <broonie@kernel.org>
To:     Pratyush Yadav <p.yadav@ti.com>
Cc:     Tudor Ambarus <tudor.ambarus@microchip.com>,
        Michael Walle <michael@walle.cc>,
        Miquel Raynal <miquel.raynal@bootlin.com>,
        Richard Weinberger <richard@nod.at>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-spi@vger.kernel.org
Subject: Re: [PATCH 4/6] spi: spi-mem: reject partial cycle transfers in
 8D-8D-8D mode
Message-ID: <20210507153132.GC6383@sirena.org.uk>
References: <20210506191829.8271-1-p.yadav@ti.com>
 <20210506191829.8271-5-p.yadav@ti.com>
 <20210507125533.GA6383@sirena.org.uk>
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On Fri, May 07, 2021 at 07:26:33PM +0530, Pratyush Yadav wrote:

> Patches 2 and 3 are a slightly different matter. They add an extra=20
> register write. But most controllers I've come across don't support=20
> 1-byte writes in 8D mode. It is likely that they are sending=20
> bogus/undefined values in the second byte and deasserting CS only after=
=20
> the cycle is done. So they should _in theory_ change undefined behaviour=
=20
> to defined behaviour.

> Still, they introduce an extra register write. I'm not sure how=20
> risk-tolerant you want to be for stable backports. I will leave the=20
> judgement to you or Tudor or Vignesh.

Ah, given that if nobody's seeing any issues I'd probably just hold off
there TBH.

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