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Sat, 8 May 2021 00:14:52 +0000 From: Liming Sun To: Vadim Pasternak , Andy Shevchenko , Darren Hart CC: "linux-kernel@vger.kernel.org" , "platform-driver-x86@vger.kernel.org" Subject: RE: [PATCH v1 1/1] platform/mellanox: mlxbf-tmfifo: Fix a memory barrier issue Thread-Topic: [PATCH v1 1/1] platform/mellanox: mlxbf-tmfifo: Fix a memory barrier issue Thread-Index: AQHXQ1Rd0aNDff8xpE27c3mU/0BwmarYJ3aAgACQCEA= Date: Sat, 8 May 2021 00:14:52 +0000 Message-ID: References: <177d12443460bc613aa495fbdbabbbeef43ba7ff.1620400475.git.limings@nvidia.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nvidia.com; dkim=none (message not signed) header.d=none;nvidia.com; dmarc=none action=none header.from=nvidia.com; x-originating-ip: [173.76.169.242] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f780dff9-30a5-4c1d-4cfe-08d911b64d28 x-ms-traffictypediagnostic: BL0PR12MB4881: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:469; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB3565.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f780dff9-30a5-4c1d-4cfe-08d911b64d28 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 May 2021 00:14:52.4133 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: oHbDwkc/r9a/SLn6LzF6vPmJtm1bsjnd43q/fR9hMS2fR3hi+JillTCKgH0RIIlWeL48d5CEuTrvGWVAW820DA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4881 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thanks!=20 Sure, I'll resent it as bugfix in v2. > -----Original Message----- > From: Vadim Pasternak > Sent: Friday, May 7, 2021 11:39 AM > To: Liming Sun ; Andy Shevchenko > ; Darren Hart > Cc: linux-kernel@vger.kernel.org; platform-driver-x86@vger.kernel.org > Subject: RE: [PATCH v1 1/1] platform/mellanox: mlxbf-tmfifo: Fix a memory > barrier issue >=20 >=20 >=20 > > -----Original Message----- > > From: Liming Sun > > Sent: Friday, May 7, 2021 6:19 PM > > To: Andy Shevchenko ; Darren Hart > > ; Vadim Pasternak > > Cc: Liming Sun ; linux-kernel@vger.kernel.org; > > platform-driver-x86@vger.kernel.org > > Subject: [PATCH v1 1/1] platform/mellanox: mlxbf-tmfifo: Fix a memory > > barrier issue > > > > The virtio framework uses wmb() when updating avail->idx. It guarantees > > the write order, but not necessarily loading order for the code accessi= ng > the > > memory. This commit adds a load barrier after reading the avail->idx to > make > > sure all the data in the descriptor is visible. It also adds a barrier = when > > returning the packet to virtio framework to make sure read/writes are > visible > > to the virtio code. >=20 > I suppose it should be sent as Bugfix? >=20 > > > > Signed-off-by: Liming Sun > > --- > > drivers/platform/mellanox/mlxbf-tmfifo.c | 11 ++++++++++- > > 1 file changed, 10 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/platform/mellanox/mlxbf-tmfifo.c > > b/drivers/platform/mellanox/mlxbf-tmfifo.c > > index bbc4e71..38800e8 100644 > > --- a/drivers/platform/mellanox/mlxbf-tmfifo.c > > +++ b/drivers/platform/mellanox/mlxbf-tmfifo.c > > @@ -294,6 +294,9 @@ static irqreturn_t mlxbf_tmfifo_irq_handler(int irq= , > > void *arg) > > if (vring->next_avail =3D=3D virtio16_to_cpu(vdev, vr->avail->idx)) > > return NULL; > > > > + /* Make sure 'avail->idx' is visible already. */ > > + virtio_rmb(false); > > + > > idx =3D vring->next_avail % vr->num; > > head =3D virtio16_to_cpu(vdev, vr->avail->ring[idx]); > > if (WARN_ON(head >=3D vr->num)) > > @@ -322,7 +325,7 @@ static void mlxbf_tmfifo_release_desc(struct > > mlxbf_tmfifo_vring *vring, > > * done or not. Add a memory barrier here to make sure the update > > above > > * completes before updating the idx. > > */ > > - mb(); > > + virtio_mb(false); > > vr->used->idx =3D cpu_to_virtio16(vdev, vr_idx + 1); } > > > > @@ -733,6 +736,12 @@ static bool mlxbf_tmfifo_rxtx_one_desc(struct > > mlxbf_tmfifo_vring *vring, > > desc =3D NULL; > > fifo->vring[is_rx] =3D NULL; > > > > + /* > > + * Make sure the load/store are in order before > > + * returning back to virtio. > > + */ > > + virtio_mb(false); > > + > > /* Notify upper layer that packet is done. */ > > spin_lock_irqsave(&fifo->spin_lock[is_rx], flags); > > vring_interrupt(0, vring->vq); > > -- > > 1.8.3.1