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Sat, 8 May 2021 11:22:43 +0000 From: Vadim Pasternak To: Liming Sun , Andy Shevchenko , Darren Hart CC: "linux-kernel@vger.kernel.org" , "platform-driver-x86@vger.kernel.org" Subject: RE: [PATCH v2] platform/mellanox: mlxbf-tmfifo: Fix a memory barrier issue Thread-Topic: [PATCH v2] platform/mellanox: mlxbf-tmfifo: Fix a memory barrier issue Thread-Index: AQHXQ6FYEXJKkcU5D0+EAyr87e3wUKrZcIGQ Date: Sat, 8 May 2021 11:22:43 +0000 Message-ID: References: <177d12443460bc613aa495fbdbabbbeef43ba7ff.1620400475.git.limings@nvidia.com> <1620433812-17911-1-git-send-email-limings@nvidia.com> In-Reply-To: <1620433812-17911-1-git-send-email-limings@nvidia.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nvidia.com; dkim=none (message not signed) header.d=none;nvidia.com; dmarc=none action=none header.from=nvidia.com; x-originating-ip: [46.117.116.151] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 584ba631-215d-4998-76ef-08d912139976 x-ms-traffictypediagnostic: DM5PR12MB2536: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:751; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3898.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 584ba631-215d-4998-76ef-08d912139976 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 May 2021 11:22:43.6782 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 4COXynrZ2wcuS2XX4kYL8uV/cS7y0BRbNW8T7+WxUONYVFNrUBTZNk2FsjdByCC6YkqyIaLnq0BWX72m+NbFrg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2536 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Liming Sun > Sent: Saturday, May 8, 2021 3:30 AM > To: Andy Shevchenko ; Darren Hart > ; Vadim Pasternak > Cc: Liming Sun ; linux-kernel@vger.kernel.org; > platform-driver-x86@vger.kernel.org > Subject: [PATCH v2] platform/mellanox: mlxbf-tmfifo: Fix a memory barrier > issue >=20 > The virtio framework uses wmb() when updating avail->idx. It guarantees > the write order, but not necessarily loading order for the code accessing= the > memory. This commit adds a load barrier after reading the avail->idx to m= ake > sure all the data in the descriptor is visible. It also adds a barrier wh= en > returning the packet to virtio framework to make sure read/writes are vis= ible > to the virtio code. >=20 > Fixes: 1357dfd7261f ("platform/mellanox: Add TmFifo driver for Mellanox > BlueField Soc") > Signed-off-by: Liming Sun Reviewed-by: Vadim Pasternak Liming, Please, next time send patch to upstream after getting official approval fr= om our internal review. In this case notes v1 -> v2 and version"v2" will be useless. Thanks, Vadim. > --- > v1->v2: > Updates for Vadim's comments: > - Add the 'Fixes' field in the commit message. > v1: Initial version > --- > drivers/platform/mellanox/mlxbf-tmfifo.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/platform/mellanox/mlxbf-tmfifo.c > b/drivers/platform/mellanox/mlxbf-tmfifo.c > index bbc4e71..38800e8 100644 > --- a/drivers/platform/mellanox/mlxbf-tmfifo.c > +++ b/drivers/platform/mellanox/mlxbf-tmfifo.c > @@ -294,6 +294,9 @@ static irqreturn_t mlxbf_tmfifo_irq_handler(int irq, > void *arg) > if (vring->next_avail =3D=3D virtio16_to_cpu(vdev, vr->avail->idx)) > return NULL; >=20 > + /* Make sure 'avail->idx' is visible already. */ > + virtio_rmb(false); > + > idx =3D vring->next_avail % vr->num; > head =3D virtio16_to_cpu(vdev, vr->avail->ring[idx]); > if (WARN_ON(head >=3D vr->num)) > @@ -322,7 +325,7 @@ static void mlxbf_tmfifo_release_desc(struct > mlxbf_tmfifo_vring *vring, > * done or not. Add a memory barrier here to make sure the update > above > * completes before updating the idx. > */ > - mb(); > + virtio_mb(false); > vr->used->idx =3D cpu_to_virtio16(vdev, vr_idx + 1); } >=20 > @@ -733,6 +736,12 @@ static bool mlxbf_tmfifo_rxtx_one_desc(struct > mlxbf_tmfifo_vring *vring, > desc =3D NULL; > fifo->vring[is_rx] =3D NULL; >=20 > + /* > + * Make sure the load/store are in order before > + * returning back to virtio. > + */ > + virtio_mb(false); > + > /* Notify upper layer that packet is done. */ > spin_lock_irqsave(&fifo->spin_lock[is_rx], flags); > vring_interrupt(0, vring->vq); > -- > 1.8.3.1