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Sat, 8 May 2021 16:33:15 +0000 Subject: Re: [RFC 1/2] vfio/pci: keep the prefetchable attribute of a BAR region in VMA To: Catalin Marinas , Will Deacon CC: Vikram Sethi , Alex Williamson , Mark Kettenis , "Marc Zyngier" , "christoffer.dall@arm.com" , "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.cs.columbia.edu" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , Jason Sequeira References: <878s4zokll.wl-maz@kernel.org> <87eeeqvm1d.wl-maz@kernel.org> <87bl9sunnw.wl-maz@kernel.org> <20210503084432.75e0126d@x1.home.shazbot.org> <20210504083005.GA12290@willie-the-truck> <20210505180228.GA3874@arm.com> From: Shanker R Donthineni Message-ID: <273ba1c2-dfe6-7dc1-3e40-03398e82469b@nvidia.com> Date: Sat, 8 May 2021 11:33:11 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210505180228.GA3874@arm.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Content-Language: en-US X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1933258b-34ed-4da5-1154-08d9123efcb0 X-MS-TrafficTypeDiagnostic: DM6PR12MB3705: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 May 2021 16:33:18.4566 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1933258b-34ed-4da5-1154-08d9123efcb0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3705 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marc, On 5/5/21 1:02 PM, Catalin Marinas wrote: >>> Will/Catalin, perhaps you could explain your thought process on why you chose >>> Normal NC for ioremap_wc on the armv8 linux port instead of Device GRE or other >>> Device Gxx. >> I think a combination of: compatibility with 32-bit Arm, the need to >> support unaligned accesses and the potential for higher performance. > IIRC the _wc suffix also matches the pgprot_writecombine() used by some > drivers to map a video framebuffer into user space. Accesses to the > framebuffer are not guaranteed to be aligned (memset/memcpy don't ensure > alignment on arm64 and the user doesn't have a memset_io or memcpy_toio). > >> Furthermore, ioremap() already gives you a Device memory type, and we're >> tight on MAIR space. > We have MT_DEVICE_GRE currently reserved though no in-kernel user, we > might as well remove it. @Marc, Could you provide your thoughts/guidance for the next step? The proposal of getting hints for prefetchable regions from VFIO/QEMU is not recommended, The only option left is to implement ARM64 dependent logic in KVM. Option-1: I think we could take advantage of stage-1/2 combining rules to allow NORMAL_NC memory-type for device memory in VM. Always map device memory at stage-2 as NORMAL-NC and trust VM's stage-1 MT. --------------------------------------------------------------- Stage-2 MT     Stage-1 MT    Resultant MT (combining-rules/FWB) --------------------------------------------------------------- Normal-NC      Normal-WT           Normal-NC    -           Normal-WB              -    -           Normal-NC              -    -           Device-       Device- --------------------------------------------------------------- We've been using this option internally for testing purpose and validated with NVME/Mellanox/GPU pass-through devices on Marvell-Thundex2 platform. Option-2: Get resource properties associated with MMIO using lookup_resource() and map at stage-2 as Normal-NC if IORESOURCE_PREFETCH is set in flags.