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From:   Linus Walleij <linus.walleij@linaro.org>
Date:   Sun, 9 May 2021 02:27:40 +0200
Message-ID: <CACRpkdb=0EQN=CJqfjKS-iuAiKCvU38fw5krzEY5LvhNpyFd3w@mail.gmail.com>
Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: Add DT bindings for apple,pinctrl
To:     Mark Kettenis <mark.kettenis@xs4all.nl>
Cc:     kettenis@openbsd.org, Krzysztof Kozlowski <krzk@kernel.org>,
        Tomasz Figa <tomasz.figa@gmail.com>,
        Marc Zyngier <maz@kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>, Hector Martin <marcan@marcan.st>,
        Rob Herring <robh+dt@kernel.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        Bartosz Golaszewski <bgolaszewski@baylibre.com>,
        sven@svenpeter.dev
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On Sun, May 9, 2021 at 1:02 AM Mark Kettenis <mark.kettenis@xs4all.nl> wrote:
> [Me]
> > On Sat, May 8, 2021 at 4:20 PM Mark Kettenis <kettenis@openbsd.org> wrote:

> My U-Boot driver is here:

Thanks! Looks nice.

> > > +description: |
> > > +  The Apple GPIO controller is a simple combined pin and GPIO controller
> >
> > spelling
>
> Not sure I'm seeing a spelling mistake here.  Do you want a comma
> inserted somewhere?

Your original mail says "conroller" but the helpful google mail
editor autocorrected the mistake when I hit enter after it.

> > So is this an entirely Apple thing now, and not based on some Samsung
> > block from S3C like what we have seen before?
>
> As far as I can tell, yes.  This Apple controller has a single
> register per pin that controls the muxing and gpio functions, whereas
> the S3C controller seems to have 4 registers per pin.

Fair enough.

> > What I am really wondering is if these interrupts are hierarchical,
> > i.e. that they match 1-to-1 to a GPIO line.
>
> They don't match 1-1.  The GPIOs can be assigned to one of
> (apparently) 7 interrupt groups.

Aha so it is a 1-to-1..* thing. How delicate.

>  I haven't looked to closely at this
> yet since U-Boot doesn't need/use the interrupt capability.  But I
> suspect that pins don't have to be assigned to a interrupt group and
> that explains why there are only 7 interrupt groups as the 8th state
> is reserved for "unasigned".  The number of pins per controller
> varies, but one of them has 212 pins.

Wow.

> Multiple pins can be assigned to the same interrupt group as far as I
> can tell.  So in that case the driver will have to look at status
> bits.

OK then this is not hierarchical.

> > Marc Zyngier can probably tell the story of why it is handled
> > like this,
>
> Ok, hopefully Marc can say something sensible here, but I'd say the
> interrupts on this hardware are cascaded.

Yes looks like so, it will be an interesting interrupt driver when
you get to that.

I have only the question in my second mail (just sent) but in any
case you are not doing anything out of the ordinary (it looks very
similar to the STM32) so I'm pleased with this binding.

I wanna give the DT reviewers some time to look at it as well
but I imagine we can soon merge this.

Yours.
Linus Walleij