Message-ID: <453CCD5E.6060303@zytor.com>
Date: Mon, 23 Oct 2006 07:10:38 -0700
From: "H. Peter Anvin" <hpa@zytor.com>
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To: "Rafael J. Wysocki" <rjw@sisk.pl>
CC: Sandeep Kumar <sandeepksinha@gmail.com>, linux-kernel@vger.kernel.org
Subject: Re: PAE and PSE ??
References: <37d33d830610212329o420e0ee4i75e6bddfcf2fb772@mail.gmail.com> <200610221215.26525.rjw@sisk.pl> <453C00B7.3040909@zytor.com> <200610231213.47232.rjw@sisk.pl>
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Rafael J. Wysocki wrote:
> 
> Well, "AMD64 Architecture Programmer’s Manual" says the following:
> 
> The choice of 2 Mbyte or 4 Mbyte as the large physical-page size
> depends on the value of CR4.PSE and CR4.PAE, as follows:
> - If physical-address extensions are enabled (CR4.PAE=1), the
>    large physical-page size is 2 Mbytes, regardless of the value
>    of CR4.PSE.
> - If physical-address extensions are disabled (CR4.PAE=0)
>    and CR4.PSE=1, the large physical-page size is 4 Mbytes.
> - If both CR4.PAE=0 and CR4.PSE=0, the only available page
>    size is 4 Kbytes.
> 

That would be a retroactive redef on the part of AMD; it probably makes 
sense for x86-64 if someone thinks that is may drop support for 4 MB 
pages at some point in the distant future.  Still, I'm not sure Intel 
would agree with the definition as stated, although I haven't looked in 
the docs.

This is all extremely theoretical, since there has never been a chip 
with PAE=1 and PSE=0, and I wouldn't expect one to appear any time soon.

	-hpa
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