From: "Rafael J. Wysocki" <rjw@sisk.pl>
To: "H. Peter Anvin" <hpa@zytor.com>
Subject: Re: PAE and PSE ??
Date: Mon, 23 Oct 2006 16:14:05 +0200
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Cc: Sandeep Kumar <sandeepksinha@gmail.com>, linux-kernel@vger.kernel.org
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On Monday, 23 October 2006 16:10, H. Peter Anvin wrote:
> Rafael J. Wysocki wrote:
> > 
> > Well, "AMD64 Architecture Programmer’s Manual" says the following:
> > 
> > The choice of 2 Mbyte or 4 Mbyte as the large physical-page size
> > depends on the value of CR4.PSE and CR4.PAE, as follows:
> > - If physical-address extensions are enabled (CR4.PAE=1), the
> >    large physical-page size is 2 Mbytes, regardless of the value
> >    of CR4.PSE.
> > - If physical-address extensions are disabled (CR4.PAE=0)
> >    and CR4.PSE=1, the large physical-page size is 4 Mbytes.
> > - If both CR4.PAE=0 and CR4.PSE=0, the only available page
> >    size is 4 Kbytes.
> > 
> 
> That would be a retroactive redef on the part of AMD; it probably makes 
> sense for x86-64 if someone thinks that is may drop support for 4 MB 
> pages at some point in the distant future.  Still, I'm not sure Intel 
> would agree with the definition as stated, although I haven't looked in 
> the docs.
> 
> This is all extremely theoretical, since there has never been a chip 
> with PAE=1 and PSE=0, and I wouldn't expect one to appear any time soon.

Agreed.

Rafael


-- 
You never change things by fighting the existing reality.
		R. Buckminster Fuller
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