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Date:   Mon, 10 May 2021 16:28:33 +0530
From:   mdalam@codeaurora.org
To:     Miquel Raynal <miquel.raynal@bootlin.com>
Cc:     mani@kernel.org, boris.brezillon@collabora.com,
        linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
        sricharan@codeaurora.org
Subject: Re: [PATCH] mtd: rawnand: qcom: avoid write to obsolete register
In-Reply-To: <20210504085805.73e60979@xps13>
References: <1619205694-25645-1-git-send-email-mdalam@codeaurora.org>
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 <20210504085805.73e60979@xps13>
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On 2021-05-04 12:28, Miquel Raynal wrote:
> Hello,
> 
> mdalam@codeaurora.org wrote on Mon, 03 May 2021 20:24:54 +0530:
> 
>> On 2021-04-24 00:51, Md Sadre Alam wrote:
>> > QPIC_EBI2_ECC_BUF_CFG register got obsolete from QPIC V2.0 onwards.
>> > Avoid writing this register if QPIC version is V2.0 or newer.
>> >
>> > Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
>> > ---
>> >  drivers/mtd/nand/raw/qcom_nandc.c | 17 +++++++++++------
>> >  1 file changed, 11 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
>> > b/drivers/mtd/nand/raw/qcom_nandc.c
>> > index fd4c318..8c5205c 100644
>> > --- a/drivers/mtd/nand/raw/qcom_nandc.c
>> > +++ b/drivers/mtd/nand/raw/qcom_nandc.c
>> > @@ -714,7 +714,8 @@ static void update_rw_regs(struct qcom_nand_host
>> > *host, int num_cw, bool read)
>> >  	nandc_set_reg(nandc, NAND_DEV0_CFG0, cfg0);
>> >  	nandc_set_reg(nandc, NAND_DEV0_CFG1, cfg1);
>> >  	nandc_set_reg(nandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
>> > -	nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
>> > +	if (!nandc->props->qpic_v2)
>> > +		nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
>> >  	nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
>> >  	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
>> >  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>> > @@ -1083,7 +1084,8 @@ static void config_nand_page_read(struct
>> > qcom_nand_controller *nandc)
>> >  {
>> >  	write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>> >  	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> > -	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>> > +	if (!nandc->props->qpic_v2)
>> > +		write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>> >  	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
>> >  	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
>> >  		      NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
>> > @@ -1132,8 +1134,9 @@ static void config_nand_page_write(struct
>> > qcom_nand_controller *nandc)
>> >  {
>> >  	write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>> >  	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> > -	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
>> > -		      NAND_BAM_NEXT_SGL);
>> > +	if (!nandc->props->qpic_v2)
>> > +		write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
>> > +			      NAND_BAM_NEXT_SGL);
>> >  }
>> >
>> >  /*
>> > @@ -1187,7 +1190,8 @@ static int nandc_param(struct qcom_nand_host > *host)
>> >  					| 2 << WR_RD_BSY_GAP
>> >  					| 0 << WIDE_FLASH
>> >  					| 1 << DEV0_CFG1_ECC_DISABLE);
>> > -	nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << > ECC_CFG_ECC_DISABLE);
>> > +	if (!nandc->props->qpic_v2)
>> > +		nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << > ECC_CFG_ECC_DISABLE);
>> >
>> >  	/* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
>> >  	if (!nandc->props->qpic_v2) {
>> > @@ -2628,7 +2632,8 @@ static int qcom_nand_attach_chip(struct nand_chip > *chip)
>> >  				| ecc_mode << ECC_MODE
>> >  				| host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
>> >
>> > -	host->ecc_buf_cfg = 0x203 << NUM_STEPS;
>> > +	if (!nandc->props->qpic_v2)
>> > +		host->ecc_buf_cfg = 0x203 << NUM_STEPS;
>> >
>> >  	host->clrflashstatus = FS_READY_BSY_N;
>> >  	host->clrreadstatus = 0xc0;
>> 
>> 
>> ping! Hi Miquel could you review this change and let me know if more 
>> info needed.
> 
> Come on, that's only 6 days of work and we are in the middle of the
> merge window...
> 
> BTW "avoid write to" in the title is incorrect "writing to" would be
> nicer.

  Updated commit message in V2 patch.
> 
> Thanks,
> Miquèl