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[109.252.193.91]) by smtp.gmail.com with ESMTPSA id k8sm2422254lfo.123.2021.05.10.16.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 16:17:43 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Rob Herring , =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v7 0/8] Couple improvements for Tegra clk driver Date: Tue, 11 May 2021 02:17:29 +0300 Message-Id: <20210510231737.30313-1-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series fixes couple minor standalone problems of the Tegra clk driver and adds new features. Changelog: v7: - Added r-b from Rob Herring to the schema patch which he gave to v6. - Dropped the MAINTAINERS-update patch. Previously Peter said on IRC that he doesn't have time on the tegra-clk driver anymore and approved the patch, but then he refused to ack the v6 patch, saying that he is not reading mailing lists. So I don't feel comfortable with that patch. Peter could send it by himself if will be necessary. - Added these new patches: clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling clk: tegra: Mark external clocks as not having reset control I sent out the new Tegra30 thermal sensor driver and now CPU clock could be throttled by the sensor hardware [1]. The first patch adds support for reporting of the throttled frequency properly. [1] https://patchwork.ozlabs.org/project/linux-tegra/list/?series=243126 During of debugging sound issues of Asus Transformer devices, I noticed that the external clocks are missing the no-reset flag. The second patch fixes it. v6: - Made a small improvement and corrected a typo in patch "Fix refcounting of gate clocks" that were spotted by Michał Mirosław. v5: - Corrected example in the schema binding to silence dt_binding_check warning. - The Tegra124 binding is factored out into standalone binding since Tegra124 has properties that aren't used by other SoCs and I couldn't figure out how to make them conditional in schema. v4: - Added new patch that converts DT bindings to schema. v3: - Added acks from Thierry Reding that he gave to v2. - Added new patch "clk: tegra: Don't allow zero clock rate for PLLs". v2: - Added these new patches: clk: tegra: Halve SCLK rate on Tegra20 MAINTAINERS: Hand Tegra clk driver to Jon and Thierry v1: - Collected clk patches into a single series. Dmitry Osipenko (8): clk: tegra30: Use 300MHz for video decoder by default clk: tegra: Fix refcounting of gate clocks clk: tegra: Ensure that PLLU configuration is applied properly clk: tegra: Halve SCLK rate on Tegra20 clk: tegra: Don't allow zero clock rate for PLLs clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling clk: tegra: Mark external clocks as not having reset control dt-bindings: clock: tegra: Convert to schema .../bindings/clock/nvidia,tegra114-car.txt | 63 ---------- .../bindings/clock/nvidia,tegra124-car.txt | 107 ---------------- .../bindings/clock/nvidia,tegra124-car.yaml | 115 ++++++++++++++++++ .../bindings/clock/nvidia,tegra20-car.txt | 63 ---------- .../bindings/clock/nvidia,tegra20-car.yaml | 69 +++++++++++ .../bindings/clock/nvidia,tegra210-car.txt | 56 --------- .../bindings/clock/nvidia,tegra30-car.txt | 63 ---------- drivers/clk/tegra/clk-periph-gate.c | 72 +++++++---- drivers/clk/tegra/clk-periph.c | 11 ++ drivers/clk/tegra/clk-pll.c | 12 +- drivers/clk/tegra/clk-tegra-periph.c | 6 +- drivers/clk/tegra/clk-tegra-super-cclk.c | 16 ++- drivers/clk/tegra/clk-tegra20.c | 6 +- drivers/clk/tegra/clk-tegra30.c | 4 +- 14 files changed, 271 insertions(+), 392 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt -- 2.30.2