Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp3127823pxj; Mon, 10 May 2021 19:46:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzI5u2LA8y8RhlSl357fYz8Z/J+kV0Cd7qwSFBU3z+graZCAbiri/yvjsr+/2ur/YjftwEE X-Received: by 2002:a17:906:4159:: with SMTP id l25mr29241060ejk.76.1620701205559; Mon, 10 May 2021 19:46:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620701205; cv=none; d=google.com; s=arc-20160816; b=IbopK6XZ5f8quG3YvlPKCDSx9tahz3HVBQ8fyTY6LhZYbOqqLW3zR97zNWS+ZQr9vv eSfViQlTOmFW+38yW54m7tO7+k4u/UV1fUy4MG4xgIYH7piXvVPcgZMnqSpDo8gxtKIg lrPnE/9CBeXUeX/BZNQZjNzvSqvqadUkLn98WukX6v+gQRphv43fcnDjRwk48q/jQvcv p/7E/SN4tyLTy3rV03ehi32eZPdA5gxAks5uyGrRXB6OdXfC0qtjabEpN1fSKXeHgBLK txkDSmz6XtLuLzYKDL1qnetqoORkqK5bvWqn8IWfM56CzW1HNeqkmW+GOslBA5BkDfUL 8WhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :ironport-sdr:ironport-sdr; bh=cE6qKw6Q13/3nULAhHIWkEE64xSQYoxdsLGJ1hNq49w=; b=NGKST6XZPOeTAWlTKTcF2MiYYILX0lYK8J6/mJd6Vxu+VIA2sQLTf59jtgNfsHBF/L 2ksy9FuLA5teHgcCiER3vVVBq5ui47dYfl/oNpsLAPQdXCUU7IlpdCP6V1xOtYXEvLFX 1fGVZbz6HB7zGwAD5xpNyipYNxt7syuehm4GHihU08irIRBvJciZivGtNlUPYQEoHFI4 5mgPK84/H0BenjWBo7R6wrssdaDhAgg+GivkVNitx6gUgsqPfIQzb3LcJu2wE9SrmJg1 PwWCajfdL79A/Ebh1EqdrA7q6tND3goEtXxXYcZLfyPPUU1k5hww7n3aIE6cHvs9zdC8 p5Og== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y8si12420988edq.378.2021.05.10.19.46.22; Mon, 10 May 2021 19:46:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230403AbhEKCpI (ORCPT + 99 others); Mon, 10 May 2021 22:45:08 -0400 Received: from mga14.intel.com ([192.55.52.115]:39588 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230393AbhEKCpB (ORCPT ); Mon, 10 May 2021 22:45:01 -0400 IronPort-SDR: 2h9fQe0yD1g7CRg5Jcu6zp4vCJnsu4VnHzjl5xW7+63B8eecDyAY1Uh8nJgqNrt6s35RkFswJf RZSvroQNez7A== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="199015643" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="199015643" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2021 19:43:55 -0700 IronPort-SDR: CWPnhc8JY2IUJAtbq+Hkodt1eE1xHglKI4TYA2iCdKmuK4Oitks78Y00JHtHi6ydrBg+HyGzAY 2d5mTG6bvgEQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="468592030" Received: from clx-ap-likexu.sh.intel.com ([10.239.48.108]) by fmsmga002.fm.intel.com with ESMTP; 10 May 2021 19:43:51 -0700 From: Like Xu To: Peter Zijlstra , Paolo Bonzini Cc: Borislav Petkov , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , weijiang.yang@intel.com, Kan Liang , ak@linux.intel.com, wei.w.wang@intel.com, eranian@google.com, liuxiangdong5@huawei.com, linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org, Like Xu Subject: [PATCH v6 13/16] KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations Date: Tue, 11 May 2021 10:42:11 +0800 Message-Id: <20210511024214.280733-14-like.xu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210511024214.280733-1-like.xu@linux.intel.com> References: <20210511024214.280733-1-like.xu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The guest PEBS will be disabled when some users try to perf KVM and its user-space through the same PEBS facility OR when the host perf doesn't schedule the guest PEBS counter in a one-to-one mapping manner (neither of these are typical scenarios). The PEBS records in the guest DS buffer are still accurate and the above two restrictions will be checked before each vm-entry only if guest PEBS is deemed to be enabled. Suggested-by: Wei Wang Signed-off-by: Like Xu --- arch/x86/events/intel/core.c | 11 +++++++++-- arch/x86/include/asm/kvm_host.h | 9 +++++++++ arch/x86/kvm/vmx/pmu_intel.c | 19 +++++++++++++++++++ arch/x86/kvm/vmx/vmx.c | 4 ++++ arch/x86/kvm/vmx/vmx.h | 1 + 5 files changed, 42 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 18843412718a..678958df2ce9 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3954,8 +3954,15 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask, }; - /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ - arr[0].guest |= arr[*nr].guest; + if (arr[*nr].host) { + /* Disable guest PEBS if host PEBS is enabled. */ + arr[*nr].guest = 0; + } else { + /* Disable guest PEBS for cross-mapped PEBS counters. */ + arr[*nr].guest &= ~pmu->host_cross_mapped_mask; + /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ + arr[0].guest |= arr[*nr].guest; + } ++(*nr); return arr; diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index b4deb7820397..15bff609fd57 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -479,6 +479,15 @@ struct kvm_pmu { u64 pebs_data_cfg; u64 pebs_data_cfg_mask; + /* + * If a guest counter is cross-mapped to host counter with different + * index, its PEBS capability will be temporarily disabled. + * + * The user should make sure that this mask is updated + * after disabling interrupts and before perf_guest_get_msrs(); + */ + u64 host_cross_mapped_mask; + /* * The gate to release perf_events not marked in * pmc_in_use only once in a vcpu time slice. diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 296246bf253d..28152d7fd12d 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -770,6 +770,25 @@ static void intel_pmu_cleanup(struct kvm_vcpu *vcpu) intel_pmu_release_guest_lbr_event(vcpu); } +void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) +{ + struct kvm_pmc *pmc = NULL; + int bit; + + for_each_set_bit(bit, (unsigned long *)&pmu->global_ctrl, + X86_PMC_IDX_MAX) { + pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, bit); + + if (!pmc || !pmc_speculative_in_use(pmc) || + !pmc_is_enabled(pmc)) + continue; + + if (pmc->perf_event && (pmc->idx != pmc->perf_event->hw.idx)) + pmu->host_cross_mapped_mask |= + BIT_ULL(pmc->perf_event->hw.idx); + } +} + struct kvm_pmu_ops intel_pmu_ops = { .find_arch_event = intel_find_arch_event, .find_fixed_event = intel_find_fixed_event, diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index df5c1c7f9bd3..e43d58020c75 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -6596,6 +6596,10 @@ static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) struct perf_guest_switch_msr *msrs; struct kvm_pmu *pmu = vcpu_to_pmu(&vmx->vcpu); + pmu->host_cross_mapped_mask = 0; + if (pmu->pebs_enable & pmu->global_ctrl) + intel_pmu_cross_mapped_check(pmu); + /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */ msrs = perf_guest_get_msrs(&nr_msrs, (void *)pmu); if (!msrs) diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 16e4e457ba23..72f1175e474b 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -96,6 +96,7 @@ union vmx_exit_reason { #define vcpu_to_lbr_desc(vcpu) (&to_vmx(vcpu)->lbr_desc) #define vcpu_to_lbr_records(vcpu) (&to_vmx(vcpu)->lbr_desc.records) +void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu); bool intel_pmu_lbr_is_compatible(struct kvm_vcpu *vcpu); bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu); -- 2.31.1