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Tue, 11 May 2021 15:26:23 +0000 From: Naveen Krishna Chatradhi To: linux-edac@vger.kernel.org, x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mingo@redhat.com, mchehab@kernel.org, Mukul Joshi Subject: [PATCH 3/3] x86/mce: Add MCE priority for Accelerator devices Date: Tue, 11 May 2021 20:55:38 +0530 Message-Id: <20210511152538.148084-3-nchatrad@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210511152538.148084-1-nchatrad@amd.com> References: <20210511152538.148084-1-nchatrad@amd.com> Content-Type: text/plain X-Originating-IP: [165.204.156.251] X-ClientProxiedBy: MA1PR0101CA0004.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::14) To DM6PR12MB4388.namprd12.prod.outlook.com (2603:10b6:5:2a9::10) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from milan-ETHANOL-X.amd.com (165.204.156.251) by MA1PR0101CA0004.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.25 via Frontend Transport; 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On some future AMD platforms, GPU devices will process MCE errors and work as error detection devices. Signed-off-by: Mukul Joshi Reviewed-by: John Clements Reviewed-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 8cbe7221a253..849f10a8602d 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -173,6 +173,7 @@ enum mce_notifier_prios { MCE_PRIO_LOWEST, MCE_PRIO_MCELOG, MCE_PRIO_EDAC, + MCE_PRIO_ACCEL, MCE_PRIO_NFIT, MCE_PRIO_EXTLOG, MCE_PRIO_UC, -- 2.17.1