Subject: Re: Ordering between PCI config space writes and MMIO reads?
From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: Roland Dreier <rdreier@cisco.com>
Cc: linux-pci@atrey.karlin.mff.cuni.cz, linux-ia64@vger.kernel.org,
       linux-kernel@vger.kernel.org, openib-general@openib.org,
       John Partridge <johnip@sgi.com>
In-Reply-To: <adafyddcysw.fsf@cisco.com>
References: <adafyddcysw.fsf@cisco.com>
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Date: Tue, 24 Oct 2006 22:24:23 +0100
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Ar Maw, 2006-10-24 am 12:13 -0700, ysgrifennodd Roland Dreier:
>  1) Is this something that should be fixed in the driver?  The PCI
>     spec allows MMIO cycles to start before an earlier config cycle
>     completed, but do we want to expose this fact to drivers?  Would
>     it be better for ia64 to use some sort of barrier to make sure
>     pci_write_config_xxx() is strongly ordered with MMIO?

It is good to be conservative in this area. Some AMD chipsets at least
had ordering problems with some configurations in the K7 era.


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