To: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: linux-pci@atrey.karlin.mff.cuni.cz, linux-ia64@vger.kernel.org,
       linux-kernel@vger.kernel.org, openib-general@openib.org,
       John Partridge <johnip@sgi.com>
Subject: Re: Ordering between PCI config space writes and MMIO reads?
References: <adafyddcysw.fsf@cisco.com>
	<1161725063.22348.39.camel@localhost.localdomain>
From: Roland Dreier <rdreier@cisco.com>
Date: Tue, 24 Oct 2006 14:29:47 -0700
In-Reply-To: <1161725063.22348.39.camel@localhost.localdomain> (Alan Cox's message of "Tue, 24 Oct 2006 22:24:23 +0100")
Message-ID: <aday7r5bdx0.fsf@cisco.com>
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 > It is good to be conservative in this area. Some AMD chipsets at least
 > had ordering problems with some configurations in the K7 era.

Could you expand a little?  Do you mean that the arch implementation
of pci_write_config_xxx() should have extra barriers, or that drivers
should do belt-and-suspenders flushes to make sure config writes are
really done properly?

 - R.
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