Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1422628AbWJXVhr (ORCPT ); Tue, 24 Oct 2006 17:37:47 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1161246AbWJXVhr (ORCPT ); Tue, 24 Oct 2006 17:37:47 -0400 Received: from havoc.gtf.org ([69.61.125.42]:56278 "EHLO havoc.gtf.org") by vger.kernel.org with ESMTP id S1161244AbWJXVhp (ORCPT ); Tue, 24 Oct 2006 17:37:45 -0400 Date: Tue, 24 Oct 2006 17:37:44 -0400 From: Jeff Garzik To: Roland Dreier Cc: Alan Cox , linux-pci@atrey.karlin.mff.cuni.cz, linux-ia64@vger.kernel.org, linux-kernel@vger.kernel.org, openib-general@openib.org, John Partridge Subject: Re: Ordering between PCI config space writes and MMIO reads? Message-ID: <20061024213744.GH2043@havoc.gtf.org> References: <1161725063.22348.39.camel@localhost.localdomain> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.1i Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 837 Lines: 21 On Tue, Oct 24, 2006 at 02:29:47PM -0700, Roland Dreier wrote: > > It is good to be conservative in this area. Some AMD chipsets at least > > had ordering problems with some configurations in the K7 era. > > Could you expand a little? Do you mean that the arch implementation > of pci_write_config_xxx() should have extra barriers, or that drivers > should do belt-and-suspenders flushes to make sure config writes are > really done properly? Drivers are -already- written to assume the pci_write_config_xxx() has the requisite barriers. The fix doesn't belong in the drivers. Jeff - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/