Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp4630079pxj; Wed, 12 May 2021 09:36:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxFS6yUpJM20znaylQOEbPs1DGJLTmCooR+a7fARJ5LEnI2r/I4zCcWXOxm+GC3OGdFi5ny X-Received: by 2002:a05:6830:351:: with SMTP id h17mr1204500ote.320.1620837380492; Wed, 12 May 2021 09:36:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620837380; cv=none; d=google.com; s=arc-20160816; b=0IPgbq2KtBKRHE06/VY4nx4XwIyIAovVmE3iKjqv1z77OaiUpS1BOS19XvXCk/PHHb 6M6zYEKj5gvkaXjVQgC3Xwt0N6hPmw/FIWWMNpRrO/TjtUQXSzwPnsp7S7cOPUd0BKuP DlExPe66GvkHxddGshAhFC/nmgVYfWaFUAu3My6T5++Z0bGQ6+Gw203WZxuDfl4slrDh +BoCTEoe625NuAAsVWxLiJiTZ2rnJrsPNegoddchH7XUkNPZsm7pHDOJtRmJu/lk7UqF QFFgmGlBnMPQEF7ZALF+qIFL1j+fmDhrkT73NZz44pVX9n4iYWa9idkR9XXO+6f1haZ2 Y/ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date:dkim-signature; bh=wQuM+8vl8RXXi53GN0Bxev1KdO1+AOXUsVXjVxgXMEU=; b=mW0qPcJGtHRypIqfVa6DP14YSKrHVQBoI0S2JZTZi/uRaAICvR+hDJthcKXA28w9Db bDvmlbzLd+kGUtf/L/if7AQAck0H5Fk1aN3nUrnn6TAfyyuxkud7J4ByeBDTOZ+07QP3 61SvOX4eVpoMdNADUo6+cBXO2MApLsCp7cC/Mq1ZEKzBFtFYIfMZVE+LYAGFcabxcVfj /JXZXYRm0Z7dObFyr033ozmUMmSNBqwWObaAAb26OcmFQf5uXa1PhKZbbnMNXpiuX2Tz wQz2N2MBhrJeNOKbQvnH6pyZ/wPXg+BVB1+DlWKVSM8SVs/lgYv2w/gXSTnSEDHE14TH UYhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@google.com header.s=20161025 header.b=Gk8wYyrG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a25si348043otp.176.2021.05.12.09.36.04; Wed, 12 May 2021 09:36:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20161025 header.b=Gk8wYyrG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236145AbhELQcR (ORCPT + 99 others); Wed, 12 May 2021 12:32:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233613AbhELPlK (ORCPT ); Wed, 12 May 2021 11:41:10 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 141B8C034625 for ; Wed, 12 May 2021 08:19:03 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id pf4-20020a17090b1d84b029015ccffe0f2eso440458pjb.0 for ; Wed, 12 May 2021 08:19:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=wQuM+8vl8RXXi53GN0Bxev1KdO1+AOXUsVXjVxgXMEU=; b=Gk8wYyrGJM70yGgKGKycvu8PnplDnEkH+5OEJt1C22vqGyiKdmOFlPZPA4wckvHBET axKUrRx6NchuLk8scPXGEtyWZbrMUjktcZzI6IZPZASxILpdMBJY9viFlOVfgQP+1ofj 8ivalJAblF5A9U1KeFVPm+l1DehzV8utNI6wKbpOuN7sn4EZN8l3nmYK2Ha5b48ec5bb PkHE+RTHRPw+V6q8eeejDJZEcjybkgbXPBTAM2+IDQN41aZzgX59kh/WAZuc3y+C8UdB J2rzs7xhcqLwFjt6Y8n8OyNF+VMCIidkgeRuEkVzMx5kEVTsP34xSAFxgk40tFKJQiJ0 dlug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=wQuM+8vl8RXXi53GN0Bxev1KdO1+AOXUsVXjVxgXMEU=; b=UYEMP3R4jt2UlcCn87PXEeffAy1HKftM31+1xTo4DGKGCVieOLXrt+M/civ4Kza6Yb FMio9eYNRP6b6GJ+IzEBRGXmNKRsylsgLbCdqjYhT3gu2iOzYujbfTpAdyn/Cwrm9iXi JP/0/Him5AqSFivixO9+1qZ+MdgL/0YT02QHWpxA3/J0utUAWgKnu+aSe7//ss/HfBVN LfMaSDMXPUQU5q0oLxwk2IrNiM9dati9cgg/Zi7FQ/4JXDdgHQnZMDCw9XbENgNX1ENZ fSbpUzTQZg75Eh1+MmaG19+FASA8YUZZmKkYVpwhcmdfKLwTPpnlwxieYAFJCT3/X+1T ApHA== X-Gm-Message-State: AOAM532jdIx1ud56C3K/LnzapXcnvxBRArl89XNnZmngXqvnD78AupPu x3TTDXaLYFuQqSOrRdC6tdYoXg== X-Received: by 2002:a17:90a:4503:: with SMTP id u3mr41532313pjg.214.1620832742442; Wed, 12 May 2021 08:19:02 -0700 (PDT) Received: from google.com (240.111.247.35.bc.googleusercontent.com. [35.247.111.240]) by smtp.gmail.com with ESMTPSA id m3sm174335pfh.174.2021.05.12.08.19.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 May 2021 08:19:01 -0700 (PDT) Date: Wed, 12 May 2021 15:18:58 +0000 From: Sean Christopherson To: "Xu, Like" Cc: Venkatesh Srinivas , Peter Zijlstra , Paolo Bonzini , Borislav Petkov , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , weijiang.yang@intel.com, Kan Liang , ak@linux.intel.com, wei.w.wang@intel.com, eranian@google.com, liuxiangdong5@huawei.com, linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org, Yao Yuan , Like Xu Subject: Re: [PATCH v6 04/16] KVM: x86/pmu: Set MSR_IA32_MISC_ENABLE_EMON bit when vPMU is enabled Message-ID: References: <20210511024214.280733-1-like.xu@linux.intel.com> <20210511024214.280733-5-like.xu@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 12, 2021, Xu, Like wrote: > Hi Venkatesh Srinivas, > > On 2021/5/12 9:58, Venkatesh Srinivas wrote: > > On 5/10/21, Like Xu wrote: > > > On Intel platforms, the software can use the IA32_MISC_ENABLE[7] bit to > > > detect whether the processor supports performance monitoring facility. > > > > > > It depends on the PMU is enabled for the guest, and a software write > > > operation to this available bit will be ignored. > > Is the behavior that writes to IA32_MISC_ENABLE[7] are ignored (rather than #GP) > > documented someplace? > > The bit[7] behavior of the real hardware on the native host is quite > suspicious. Ugh. Can you file an SDM bug to get the wording and accessibility updated? The current phrasing is a mess: Performance Monitoring Available (R) 1 = Performance monitoring enabled. 0 = Performance monitoring disabled. The (R) is ambiguous because most other entries that are read-only use (RO), and the "enabled vs. disabled" implies the bit is writable and really does control the PMU. But on my Haswell system, it's read-only. Assuming the bit is supposed to be a read-only "PMU supported bit", the SDM should be: Performance Monitoring Available (RO) 1 = Performance monitoring supported. 0 = Performance monitoring not supported. And please update the changelog to explain the "why" of whatever the behavior ends up being. The "what" is obvious from the code. > To keep the semantics consistent and simple, we propose ignoring write > operation in the virtualized world, since whether or not to expose PMU is > configured by the hypervisor user space and not by the guest side. Making up our own architectural behavior because it's convient is not a good idea. > > > diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c > > > index 9efc1a6b8693..d9dbebe03cae 100644 > > > --- a/arch/x86/kvm/vmx/pmu_intel.c > > > +++ b/arch/x86/kvm/vmx/pmu_intel.c > > > @@ -488,6 +488,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) > > > if (!pmu->version) > > > return; > > > > > > + vcpu->arch.ia32_misc_enable_msr |= MSR_IA32_MISC_ENABLE_EMON; Hmm, normally I would say overwriting the guest's value is a bad idea, but if the bit really is a read-only "PMU supported" bit, then this is the correct behavior, albeit weird if userspace does a late CPUID update (though that's weird no matter what). > > > perf_get_x86_pmu_capability(&x86_pmu); > > > > > > pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters, > > > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > > > index 5bd550eaf683..abe3ea69078c 100644 > > > --- a/arch/x86/kvm/x86.c > > > +++ b/arch/x86/kvm/x86.c > > > @@ -3211,6 +3211,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct > > > msr_data *msr_info) > > > } > > > break; > > > case MSR_IA32_MISC_ENABLE: > > > + data &= ~MSR_IA32_MISC_ENABLE_EMON; However, this is not. If it's a read-only bit, then toggling the bit should cause a #GP. > > > if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) > > > && > > > ((vcpu->arch.ia32_misc_enable_msr ^ data) & > > > MSR_IA32_MISC_ENABLE_MWAIT)) { > > > if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) > > > --